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data sheet july 2009 orca ort4622 field-programmable system chip (fpsc) four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm introduction lattice has developed a solution for designers who need the many advantages of fpga-based design implementation, coupled with high-speed serial back- plane data transfer. the 622 mbits/s backplane trans- ceiver offers a clockless, high-speed interface for interdevice communication on a board or across a backplane. the built-in clock recovery of the ort4622 allows for higher system performance, easier-to-design clock domains in a multiboard sys- tem, and fewer signals on the backplane. network designers will bene? from the backplane transceiver as a network termination device. the backplane transceiver offers sonet scrambling/descrambling of data and streamlined sonet framing, pointer moving, and transport overhead handling, plus the programmable logic to terminate the network into proprietary systems. for non-sonet applications, all sonet functionality is hidden from the user and no prior networking knowledge is required. embedded core features implemented in an orca series 3 fpga array. allows wide range of applications for sonet net- work termination application as well as generic data moving for high-speed backplane data transfer. no knowledge of sonet/sdh needed in generic applications. simply supply data, 78 mhz clock, and a frame pulse. high-speed interface (hsi) function for clock/data recovery serial backplane data transfer without external clocks. hsi function uses lattices proven 622 mbits/s serial interface core. four-channel hsi function provides 622 mbits/s serial interface per channel for a total chip band- width of 2.5 gbits/s (full duplex). lvds i/os compliant with eia *-644, support hot insertion. 8:1 data multiplexing/demultiplexing for 77.76 mhz byte-wide data processing in fpga logic. on-chip phase-lock loop (pll) clock meets b jitter tolerance speci?ation of itu-t recommendation g.958 (0.6 ui p-p at 250 khz). powerdown option of hsi receiver on a per- channel basis. highly ef?ient implementation with only 3% over- head vs. 25% for 8b10b coding. in-band management and con?uration. streamlined pointer processor (pointer mover) for 8 khz frame alignment to system clocks. built-in boundry scan ( ieee ? 1149.1 jtag). fifos align incoming data across all four channels for sts-48 (2.5 gbits/s) operation (in quad sts-12 format). 1 + 1 protection supports sts-12/sts-48 redun- dancy by either software or hardware control for protection switching applications. * eia is a registered trademark of electronic industries associa- tion. ? ieee is a registered trademark of the institute of electrical and electronics engineers, inc. table 1. orca ort4622 available fpga logic the embedded core and interface are not included in the above gate counts. the usable gate count range from a logic-only gate count to a gate count assuming 30% of the pfus/slics being used as rams. the logic-only gate count includes each pfu/slic (counted as 108 gates per pfu/slic), including 12 gates pre-lut/ff pair (eight per pfu), and 12 gates per slc/ff pair (one per pfu). each o f the four pios per pic is counted as 16 gates (two ffs, fast-capture latch, output logic, clk drivers, and i/o buffers). pfus used a s ram are counted at four gates per bit, with each pfu capable of implementing a 32 x 4 ram (or 512 gates) per pfu. device usable system gates number of luts number of registers max user ram max user i/os array size number of pfus ort4622 60k?20k 4032 5304 64k 259 18 x 28 504
table of contents contents page contents page orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 lattice semiconductor 2 discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm introduction ............................................................... 1 embedded core features ......................................... 1 fpsc highlights ........................................................ 3 software support ....................................................... 3 description ................................................................ 4 what is an fpsc? .............................................. 4 fpsc overview .................................................. 4 fpsc gate counting .......................................... 4 fpga/embedded core interface ........................ 4 isplever development system ........................ 4 fpsc design kit ................................................. 5 fpga logic overview ........................................ 5 plc logic ............................................................ 5 pic logic ............................................................ 6 system features ................................................ 6 routing ............................................................... 6 configuration ...................................................... 6 more series 3 information .................................. 6 ort4622 overview ................................................... 7 device layout ..................................................... 7 backplane transceiver interface ........................ 7 hsi interface ....................................................... 9 stm macrocell .................................................... 9 cpu interface ..................................................... 9 fpga interface ................................................... 9 fpsc configuration ............................................ 11 generic backplane transceiver application ............................................................... 11 backplane transceiver core detailed description .... 12 hsi macro ........................................................... 12 stm transmitter (fpga -> backplane) .............. 14 stm receiver (backplane -> fpga) .................. 18 powerdown mode ............................................... 24 redundancy and protection switching ............... 24 memory map ............................................................. 25 definition of register types ............................... 25 memory map overview ....................................... 26 powerup sequencing for ort4622 device .............. 34 fpga configuration data format ............................. 35 using isplever to generate configuration ram data ................................................................. 35 fpga configuration data frame ....................... 35 bit stream error checking ........................................ 37 fpga configuration modes ...................................... 37 absolute maximum ratings ...................................... 38 recommend operating conditions ........................... 38 electrical characteristics ........................................... 39 hsi circuit specifications .......................................... 40 input data ........................................................... 40 jitter tolerance ................................................... 40 generated output jitter ...................................... 40 pll ..................................................................... 40 input reference clock ........................................ 40 power supply decoupling lc circuit .................. 41 lvds i/o ................................................................... 42 lvds receiver buffer requirements ................. 43 timing characteristics ............................................... 44 description .......................................................... 44 pfu timing ......................................................... 45 plc timing ......................................................... 45 slic timing ........................................................ 45 pio timing .......................................................... 45 special function timing ..................................... 45 clock timing ....................................................... 45 configuration timing ........................................... 45 readback timing ................................................ 45 input/output buffer measurement conditions (on-lvds buffer) ...................................................... 55 fpga output buffer characteristics ......................... 56 lvds buffer characteristics ...................................... 57 termination resistor ........................................... 57 lvds driver buffer capabilities .......................... 57 estimating power dissipation .................................... 58 ort4622 clock power ....................................... 58 pin information .......................................................... 59 package thermal characteristics summary ............. 74 ja ..................................................................... 74 jc ..................................................................... 74 jc ..................................................................... 74 jb ..................................................................... 74 fpga maximum junction temperature ............. 74 package thermal characteristics ............................. 75 package coplanarity ................................................. 75 package parasitics .................................................... 75 package outline diagrams ........................................ 77 terms and definitions ......................................... 77 432-pin ebga .................................................... 78 ordering information ................................................. 79
orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 3 lattice semiconductor discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm embedded core features (continued) pseudo-sonet protocol including a1/a2 framing. sonet scrambling and descrambling for required ones density (optional). selected transport overhead (toh) bytes insertion and extraction for interdevice communication via the toh serial link. fpsc highlights implemented as an embedded core in the orca series 3+ fpsc architecture. allows the user to integrate the core with up to 120k gates of programmable logic (all in one device) and provides up to 242 user i/os in addition to the embedded core i/o pins. fpga portion retains all of the features of the orca series 3 fpga architecture: ? high-performance, cost-effective, 0.25 ?, 5-level metal technology. ?twin-quad programmable function unit (pfu) architecture with eight 16-bit look-up tables (luts) per pfu, organized in two nibbles for use in nibble- or byte-wide functions. allows for mixed arithmetic and logic functions in a single pfu. ?softwired luts (swl) allow fast cascading of up to three levels of lut logic in a single pfu. ?supplemental logic and interconnect cell (slic) provides 3-statable buffers, up to 10-bit decoder, and pa l *-like and-or-invert (aoi) in each programmable logic cell (plc). ?up to three expressclk inputs allow extremely fast clocking of signals on- and off-chip plus access to internal general clock routing. ?dual-use microprocessor interface (mpi) can be used for con?uration, as well as for a general- purpose interface to the fpga. glueless interface to i960 ? and powerpc processors with user- con?urable address space provided. ?programmable clock manager (pcm) adjusts clock phase and duty cycle for input clock rates from 5 mhz to 120 mhz. the pcm may be com- bined with fpga logic to create complex functions, such as digital phase-locked loops, frequency counters, and frequency synthesizers or clock doublers. two pcms are provided per device. ?true internal 3-state, bidirectional buses with simple control provided by the slic. ?32 x 4 ram per pfu, con?urable as single or dual port. create large, fast ram/rom blocks (128 x 8 in only eight pfus) using the slic decoders as bank drivers. ?built-in boundary scan ( ieee 1149.1 jtag) and ts_all testability function to 3-state all i/o pins. high-speed, on-chip interface provided between fpga logic and embedded core to reduce bottle- necks typically found when interfacing off-chip. software support supported by isplever software and third-party cae tools for implementing orca series 3+ devices and simulation/timing analysis with the embedded core functions. embedded core con?uration options and simulation netlists generated by fpsc con?uration manager utility. * pa l is a trademark of advanced micro devices, inc. ? i960 is a registered trademark of intel corporation. powerpc is a registered trademark of international business machines corporation.
lattice semiconductor 4 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm description what is an fpsc? fpscs, or ?ld-programmable system chips, are devices that combine ?ld-programmable logic with asic or mask-programmed logic on a single device. fpscs provide the time to market and ?xibility of fpgas, the design effort savings of using soft intellec- tual property (ip) cores, and the speed, design density, and economy of asics. fpsc overview lattices series 3+ fpscs are created from series 3 orca fpgas. to create a series 3+ fpsc, several rows of programmable logic cells (see fpga logic overview section for fpga logic details) are removed from a series 3 orca fpga, and the area is replaced with an embedded logic core. other than replacing some fpga gates with asic gates, at greater than 10:1 ef?iency, none of the fpga functionality is changed?ll of the series 3 fpga capability is retained: mpi, pcms, boundary scan, etc. the rows of programmable logic are replaced at the bottom of the device, allowing pins on the bottom and sides of the replaced rows to be used as i/o pins for the embedded core. the remainder of the device pins retain their fpga functionality as do special function fpga pins within the embedded core area. fpsc gate counting the total gate count for an fpsc is the sum of its embedded core (standard-cell/asic gates) and its fpga gates. because fpga gates are generally expressed as a usable range with a nominal value, the total fpsc gate count is sometimes expressed in the same manner. standard-cell asic gates are, however, 10 to 25 times more silicon area ef?ient than fpga gates. therefore, an fpsc with an embedded function is gate equivalent to an fpga with a much larger gate count. fpga/embedded core interface the interface between the fpga logic and the embed- ded core is designed to look like fpga i/os from the fpga side, simplifying interface signal routing and pro- viding a uni?d approach with general fpga design. effectively, the fpga is designed as if signals were going off of the device to the embedded core, but the on-chip interface is much faster than going off-chip and requires less power. all of the delays for the interface are precharacterized and accounted for in isplever software. clock spines also can pass across the fpga/embed- ded core boundary. this allows for fast, low-skew clock- ing between the fpga and the embedded core. many of the special signals from the fpga, such as done and global set/reset, are also available to the embed- ded core, making it possible to fully integrate the embedded core with the fpga as a system. for even greater system ?xibility, fpga con?uration rams are available for use by the embedded core. this allows for user-programmable options in the embedded core, in turn allowing for greater ?xibility. multiple embedded core con?urations may be designed into a single device with user-programmable control over which con?urations are implemented, as well as the capability to change core functionality simply by recon- ?uring the device. isplever development system isplever software is used to process a design from a netlist to a con?ured fpsc. this system is used to map a design onto the orca architecture and then place and route it using isplever softwares timing- driven tools. the development system also includes interfaces to, and libraries for, other popular cae tools for design entry, synthesis, simulation, and timing anal- ysis. the isplever development system interfaces to front-end design entry tools and provides the tools to produce a con?ured fpsc. in the design ?w, the user de?es the functionality of the fpga portion of the fpsc and embedded core settings at two points in the design ?w: at design entry and at the bit stream generation stage. following design entry, the develop- ment systems map, place, and route tools translate the netlist into a routed fpsc. a static timing analysis tool is provided to determine device speed, and a back- annotated netlist can be created to allow simulation.
orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 5 lattice semiconductor discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm description (continued) timing and simulation output ?es from isplever are also compatible with many third-party analysis tools. its bit stream generator is then used to generate the con- ?uration data which is loaded into the fpscs internal con?uration ram. when using the bit stream generator, the user selects options that affect the functionality of the fpsc. com- bined with the front-end tools, isplever produces con?uration data that implements the various logic and routing options discussed in this data sheet. fpsc design kit development is facilitated by an fpsc design kit which, together with isplever and third-party synthe- sis and simulation engines, provides all software and documentation required to design and verify an fpsc implementation. included in the kit are the fpsc con- ?uration manager, hdl gate-level structural netlists, all necessary synthesis libraries, and complete online documentation. the kit's software couples with isplever, providing a seamless fpsc design envi- ronment. more information can be obtained by visiting the orca website or contacting a local sales of?e, both listed on the last page of this document. fpga logic overview orca series 3 fpga logic is a new generation of sram-based fpga logic built on the successful series 2 fpga line, with enhancements and innova- tions geared toward todays high-speed designs on a single chip. designed from the start to be synthesis friendly and to reduce place and route times while maintaining the complete routability of the orca series 2 devices, the series 3 more than doubles the logic available in each logic block and incorporates sys- tem-level features that can further reduce logic require- ments and increase system speed. orca series 3 devices contain many new patented enhancements and are offered in a variety of packages, speed grades, and temperature ranges. orca series 3 fpga logic consists of three basic ele- ments: programmable logic cells (plcs), programma- ble input/output cells (pics), and system-level features. an array of plcs is surrounded by pics. each plc contains a programmable function unit (pfu), a sup- plemental logic and interconnect cell (slic), local rout- ing resources, and con?uration ram. most of the fpga logic is performed in the pfu, but decoders, pa l -like functions, and 3-state buffering can be per- formed in the slic. the pics provide device inputs and outputs and can be used to register signals and to per- form input demultiplexing, output multiplexing, and other functions on two output signals. some of the sys- tem-level functions include the new microprocessor interface ( mpi ) and the programmable clock manager ( pcm ). plc logic each pfu within a plc contains eight 4-input (16-bit) look-up tables (luts), eight latches/?p-?ps (ffs), and one additional ?p-?p that may be used indepen- dently or with arithmetic functions. the pfu is organized in a twin-quad fashion: two sets of four luts and ffs that can be controlled indepen- dently. luts may also be combined for use in arith- metic functions using fast-carry chain logic in either 4-bit or 8-bit modes. the carry-out of either mode may be registered in the ninth ff for pipelining. each pfu may also be con?ured as a synchronous 32 x 4 single- or dual-port ram or rom. the ffs (or latches) may obtain input from lut outputs or directly from invertible pfu inputs, or they can be tied high or tied low. the ffs also have programmable clock polarity, clock enables, and local set/reset. the slic is connected to plc routing resources and to the outputs of the pfu. it contains 3-state, bidirectional buffers and logic to perform up to a 10-bit and function for decoding, or an and-or with optional invert (aoi) to perform pa l -like functions. the 3-state drivers in the slic and their direct connections to the pfu out- puts make fast, true 3-state buses possible within the fpga logic, reducing required routing and allowing for real-world system performance.
lattice semiconductor 6 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm description (continued) pic logic the series 3 pic addresses the demand for ever- increasing system clock speeds. each pic contains four programmable inputs/outputs (pios) and routing resources. on the input side, each pio contains a fast- capture latch that is clocked by an expressclk . this latch is followed by a latch/ff that is clocked by a sys- tem clock from the internal general clock routing. the combination provides for very low setup requirements and zero hold times for signals coming on-chip. it may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the sig- nals without explicitly building a demultiplexer. two input signals are available to the plc array from each pio, and the orca series 2 capability to use any input pin as a clock or other global input is maintained. on the output side of each pio, two outputs from the plc array can be routed to each output ?p-?p, and logic can be associated with each i/o pad. the output logic associated with each pad allows for multiplexing of output signals and other functions of two output sig- nals. the output ff, in combination with output signal multi- plexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. the i/o buffer associated with each pad is the same as the orca series 3 buffer. system features the series 3 also provides system-level functionality by means of its dual-use microprocessor interface (mpi) and its innovative programmable clock manager (pcm). these functional blocks allow for easy glueless system interfacing and the capability to adjust to vary- ing conditions in todays high-speed systems. since these and all other series 3 features are available in every series 3+ fpsc, they can also interface to the embedded core providing for easier system integration. routing the abundant routing resources of orca series 3 fpga logic are organized to route signals individually or as buses with related control signals. clocks are routed on a low-skew, high-speed distribution network and may be sourced from plc logic, externally from any i/o pad, or from the very fast expressclk pins. expressclks may be glitchlessly and independently enabled and disabled with a programmable control sig- nal using the stopclk feature. the improved pic rout- ing resources are now similar to the patented intra-plc routing resources and provide great ?xibility in moving signals to and from the pios. this ?xibility translates into an improved capability to route designs at the required speeds when the i/o signals have been locked to speci? pins. con?uration the fpga logics functionality is determined by inter- nal con?uration ram. the fpga logics internal ini- tialization/con?uration circuitry loads the con?uration data at powerup or under system control. the ram is loaded by using one of several con?uration modes, including serial eeprom, the microprocessor inter- face, or the embedded function core. more series 3 information for more information on series 3 fpgas, please refer to the series 3 fpga data sheet, available on the lat- tice website.
7 7 lattice semiconductor orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm ort4622 overview device layout the ort4622 fpsc provides a high-speed backplane transceiver combined with fpga logic. the device is based on a 2.5 v 3.3 v i/o or3l125b fpga. the or3l125b has a 28 x 28 array of programmable logic cells (plcs). for the ort4622, the bottom ten rows of plcs in the array were replaced with the embedded backplane transceiver core. the ort4622 embedded core comprises the hsi macrocell, the synchronous transport module (stm) macrocell, a cpu interface, and lvds i/os. the four full-duplex channels perform data transfer, scrambling/descrambling and framing at the rate of 622 mbits/s. figure 1 shows the ort4622 block diagram. table 2 shows a schematic view of the ort4622. the upper portion of the device is an 18 x 28 array of plcs surrounded on the left, top, and right by programmable input/output cells (pics). at the bottom of the plc array are the core interface cells (cics) connecting to the embedded core region. the embedded core region contains the backplane transceiver functionality of the device. it is surrounded on the left, bottom, and right by backplane transceiver dedicated i/os as well as power and special function fpga pins. also shown are the interquad routing blocks (hiq, viq) present in the series 3 fpga devices. system-level functions (located in the corners of the plc array), routing resources, and con?uration ram are not shown in table 2 . backplane transceiver interface the advantage of the ort4622 fpsc is to bring spe- ci? networking functions to an early market presence with programmable logic in fpga system. the 622 mbits/s backplane transceiver core allows the ort4622 to communicate across a backplane or on a given board at an aggregate speed of 2.5 gbits/s, pro- viding a physical medium for high-speed asynchronous serial data transfer between system devices. this device is intended for, but not limited to, connecting ter- minal equipment in sonet/sdh and atm systems. for networking applications, the ort4622 offers a pseudo sonet framer and scrambler/descrambler interface capable of frame synchronization and inser- tion/extraction of selectable transport overhead bytes and sonet scrambling and descrambling for four sts-12 (622 mbits/s) channels. the channels are syn- chronized to each other by a user-provided 8 khz frame pulse. the ort4622 also provides sts-48 (2.5 gbits/s) operation across all four channels where each channel is in sts-12 format. the pseudo-sonet framer of or4622 is designed with a reduced set of the sonet framing algorithm. the pointer processing capability is more suitable for low error rate intersystem data communication, particular for backplane trans- ceiver applications. figure 2 shows the architecture of the ort4622 backplane transceiver core. 5-8113(f) figure 1. orca ort4622 block diagram ?clock/data recovery 4 full- duplex serial channels byte- wide data fpga logic standard fpga i/os lvds 622 mbits/s data 622 mbits/s data stm ?pointer mover ?scrambling ?fifo alignment ?toh processor i/os hsi 4 4
lattice semiconductor 8 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm ort4622 overview (continued) table 2 . ort4622 array iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii pt1 pt2 pt3 pt4 pt5 pt6 pt7 pt8 pt9 pt10 pt11 pt12 pt13 pt14 pt15 pt16 pt17 pt18 pt19 pt20 pt21 pt22 pt23 pt24 pt25 pt26 pt27 pt28 iiii pl1 r1 c1 r1 c2 r1 c3 r1 c4 r1 c5 r1 c6 r1 c7 r1 c8 r1 c9 r1 c10 r1 c11 r1 c12 r1 c13 r1 c14 r1 c15 r1 c16 r1 c17 r1 c18 r1 c19 r1 c20 r1 c21 r1 c22 r1 c23 r1 c24 r1 c25 r1 c26 r1 c27 r1 c28 pr1 iiii iiii pl2 r2 c1 r2 c2 r2 c3 r2 c4 r2 c5 r2 c6 r2 c7 r2 c8 r2 c9 r2 c10 r2 c11 r2 c12 r2 c13 r2 c14 r2 c15 r2 c16 r2 c17 r2 c18 r2 c19 r2 c20 r2 c21 r2 c22 r2 c23 r2 c24 r2 c25 r2 c26 r2 c27 r2 c28 pr2 iiii iiii pl3 r3 c1 r3 c2 r3 c3 r3 c4 r3 c5 r3 c6 r3 c7 r3 c8 r3 c9 r3 c10 r3 c11 r3 c12 r3 c13 r3 c14 r3 c15 r3 c16 r3 c17 r3 c18 r3 c19 r3 c20 r3 c21 r3 c22 r3 c23 r3 c24 r3 c25 r3 c26 r3 c27 r3 c28 pr3 iiii iiii pl4 r4 c1 r4 c2 r4 c3 r4 c4 r4 c5 r4 c6 r4 c7 r4 c8 r4 c9 r4 c10 r4 c11 r4 c12 r4 c13 r4 c14 r4 c15 r4 c16 r4 c17 r4 c18 r4 c19 r4 c20 r4 c21 r4 c22 r4 c23 r4 c24 r4 c25 r4 c26 r4 c27 r4 c28 pr4 iiii iiii pl5 r5 c1 r5 c2 r5 c3 r5 c4 r5 c5 r5 c6 r5 c7 r5 c8 r5 c9 r5 c10 r5 c11 r5 c12 r5 c13 r5 c14 r5 c15 r5 c16 r5 c17 r5 c18 r5 c19 r5 c20 r5 c21 r5 c22 r5 c23 r5 c24 r5 c25 r5 c26 r5 c27 r5 c28 pr5 iiii iiii pl6 r6 c1 r6 c2 r6 c3 r6 c4 r6 c5 r6 c6 r6 c7 r6 c8 r6 c9 r6 c10 r6 c11 r6 c12 r6 c13 r6 c14 r6 c15 r6 c16 r6 c17 r6 c18 r6 c19 r6 c20 r6 c21 r6 c22 r6 c23 r6 c24 r6 c25 r6 c26 r6 c27 r6 c28 pr6 iiii iiii pl7 r7 c1 r7 c2 r7 c3 r7 c4 r7 c5 r7 c6 r7 c7 r7 c8 r7 c9 r7 c10 r7 c11 r7 c12 r7 c13 r7 c14 r7 c15 r7 c16 r7 c17 r7 c18 r7 c19 r7 c20 r7 c21 r7 c22 r7 c23 r7 c24 r7 c25 r7 c26 r7 c27 r7 c28 pr7 iiii iiii pl8 r8 c1 r8 c2 r8 c3 r8 c4 r8 c5 r8 c6 r8 c7 r8 c8 r8 c9 r8 c10 r8 c11 r8 c12 r8 c13 r8 c14 r8 c15 r8 c16 r8 c17 r8 c18 r8 c19 r8 c20 r8 c21 r8 c22 r8 c23 r8 c24 r8 c25 r8 c26 r8 c27 r8 c28 pr8 iiii iiii pl9 r9 c1 r9 c2 r9 c3 r9 c4 r9 c5 r9 c6 r9 c7 r9 c8 r9 c9 r9 c10 r9 c11 r9 c12 r9 c13 r9 c14 r9 c15 r9 c16 r9 c17 r9 c18 r9 c19 r9 c20 r9 c21 r9 c22 r9 c23 r9 c24 r9 c25 r9 c26 r9 c27 r9 c28 pr9 iiii iiii pl10 r10 c1 r10 c2 r10 c3 r10 c4 r10 c5 r10 c6 r10 c7 r10 c8 r10 c9 r10 c10 r10 c11 r10 c12 r10 c13 r10 c14 r10 c15 r10 c16 r10 c17 r10 c18 r10 c19 r10 c20 r10 c21 r10 c22 r10 c23 r10 c24 r10 c25 r10 c26 r10 c27 r10 c28 pr10 iiii iiii pl11 r11 c1 r11 c2 r11 c3 r11 c4 r11 c5 r11 c6 r11 c7 r11 c8 r11 c9 r11 c10 r11 c11 r11 c12 r11 c13 r11 c14 r11 c15 r11 c16 r11 c17 r11 c18 r11 c19 r11 c20 r11 c21 r11 c22 r11 c23 r11 c24 r11 c25 r11 c26 r11 c27 r11 c28 pr11 iiii iiii pl12 r12 c1 r12 c2 r12 c3 r12 c4 r12 c5 r12 c6 r12 c7 r12 c8 r12 c9 r12 c10 r12 c11 r12 c12 r12 c13 r12 c14 r12 c15 r12 c16 r12 c17 r12 c18 r12 c19 r12 c20 r12 c21 r12 c22 r12 c23 r12 c24 r12 c25 r12 c26 r12 c27 r12 c28 pr12 iiii iiii pl13 r13 c1 r13 c2 r13 c3 r13 c4 r13 c5 r13 c6 r13 c7 r13 c8 r13 c9 r13 c10 r13 c11 r13 c12 r13 c13 r13 c14 r13 c15 r13 c16 r13 c17 r13 c18 r13 c19 r13 c20 r13 c21 r13 c22 r13 c23 r13 c24 r13 c25 r13 c26 r13 c27 r13 c28 pr13 iiii iiii pl14 r14 c1 r14 c2 r14 c3 r14 c4 r14 c5 r14 c6 r14 c7 r14 c8 r14 c9 r14 c10 r14 c11 r14 c12 r14 c13 r14 c14 r14 c15 r14 c16 r14 c17 r14 c18 r14 c19 r14 c20 r14 c21 r14 c22 r14 c23 r14 c24 r14 c25 r14 c26 r14 c27 r14 c28 pr14 iiii iiii pl15 r15 c1 r15 c2 r15 c3 r15 c4 r15 c5 r15 c6 r15 c7 r15 c8 r15 c9 r15 c10 r15 c11 r15 c12 r15 c13 r15 c14 r15 c15 r15 c16 r15 c17 r15 c18 r15 c19 r15 c20 r15 c21 r15 c22 r15 c23 r15 c24 r15 c25 r15 c26 r15 c27 r15 c28 pr15 iiii iiii pl16 r16 c1 r16 c2 r16 c3 r16 c4 r16 c5 r16 c6 r16 c7 r16 c8 r16 c9 r16 c10 r16 c11 r16 c12 r16 c13 r16 c14 r16 c15 r16 c16 r16 c17 r16 c18 r16 c19 r16 c20 r16 c21 r16 c22 r16 c23 r16 c24 r16 c25 r16 c26 r16 c27 r16 c28 pr16 iiii iiii pl17 r17 c1 r17 c2 r17 c3 r17 c4 r17 c5 r17 c6 r17 c7 r17 c8 r17 c9 r17 c10 r17 c11 r17 c12 r17 c13 r17 c14 r17 c15 r17 c16 r17 c17 r17 c18 r17 c19 r17 c20 r17 c21 r17 c22 r17 c23 r17 c24 r17 c25 r17 c26 r17 c27 r17 c28 pr17 iiii iiii pl18 r18 c1 r18 c2 r18 c3 r18 c4 r18 c5 r18 c6 r18 c7 r18 c8 r18 c9 r18 c10 r18 c11 r18 c12 r18 c13 r18 c14 r18 c15 r18 c16 r18 c17 r18 c18 r18 c19 r18 c20 r18 c21 r18 c22 r18 c23 r18 c24 r18 c25 r18 c26 r18 c27 r18 c28 pr18 iiii ii asb1 asb2 asb3 asb4 asb5 asb6 asb7 asb8 asb9 asb10 asb11 asb12 asb13 asb14 asb15 asb16 asb17 asb18 asb19 asb20 asb21 asb22 asb23 asb24 asb25 asb26 asb27 a sb28 ii ii embedded core area ii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii iiii
orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 9 lattice semiconductor discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm ort4622 overview (continued) hsi interface the high-speed interconnect (hsi) macrocell is used for clock/data recovery and mux/demux between 77.76 mhz byte-wide internal data buses and 622 mbits/s external serial links. the hsi interface receives four 622 mbits/s serial input data streams from the lvds inputs and provides four independent 77.76 mhz byte-wide data streams and recovered clock to the stm macro. there is no require- ment for bit alignment since sonet type framing will take place inside the ort4622 core. for transmit, the hsi converts four byte-wide 77.76 mhz data streams to serial streams at 622 mbits/s at the lvds outputs. stm macrocell the stm portion of the embedded core consists of transmitter (tx) and receiver (rx) sections. the receiver receives four byte-wide data streams at 77.76 mhz and the associated clocks from the hsi. in the rx section, the incoming streams are sonet framed and descrambled before they are written into a fifo which absorbs phase and delay variations and allows the shift to the system clock. the toh is then extracted and sent out on the four serial ports. the pointer mover consists of three blocks: pointer inter- preter, elastic store, and pointer generator. the pointer interpreter ?ds the synchronous transport signal (sts) synchronous payload envelopes (spe) and places it into a small elastic store from which the pointer generator will produce four byte-wide sts-12 streams of data that are aligned to the system timing pulse. in the tx section, transmitted data for each channel is received through a parallel bus and a serial port from the fpga circuit. toh bytes are received from the serial input port and can be optionally inserted from programmable registers or serial inputs to the sts-12 frame via the toh processor. each of the four parallel input buses is synchronized to a free-running system clock. then the spe and toh data is transferred to the hsi. the stm macrocell also has a scrambler/descrambler disable feature, allowing the user to disable the scram- bler of the transmitter and the descrambler of the receiver. also, unused channels can be disabled to reduce power dissipation. cpu interface the embedded core has a dedicated, asynchronous, mpc860 compatible, cpu interface that is used for de- vice setup, control, and monitoring. dual sets of i/o pins of this cpu interface with a bit stream con?urable scheme provide designers a convenient and ?xible op- tion for con?uration. one set of cpu i/o pins goes off chip allowing direct connection with an onboard cpu. another set of cpu i/o pins is available to the fpga logic allowing for a stand-alone system free of an exter- nal cpu interface, or for itegration into the series 3 fpga mpi interface. the cpu interface is composed of an 8-bit data bus, a 7-bit address bus, a chip select signal, a read/write sig- nal, and an interrupt signal. fpga interface the fpga logic will receive/transmit frame-aligned streams of 77.76 mhz data (maximum of four streams in each direction) from/to the backplane transceiver embedded core. all frames transmitted to the fpga will be aligned to the fpga frame pulse which will be provided by the fpga users logic to the stm macro. all frames received from the fpga logic will be aligned to the system frame pulse that will be supplied to the stm macro from the fpga users logic.
lattice semiconductor 10 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm ort4622 overview (continued) 5-8576 (f) figure 2. architecture of ort4622 backplane transceiver tx toh processor frame proc. tx ch a (macro) tx toh processor frame proc. tx ch b (macro) tx toh processor frame proc. tx ch d (macro) tx toh processor frame proc. tx ch c (macro) line lbpk (soft ctl) to rx toh proc. quad channel transmitter /8 pll rx ch a (macrocell) 77.76 mhz fifo pointer mover sts48 ch a rx ch b (macrocell) 77.76 mhz ch b rx ch c (macrocell) 77.76 mhz ch c rx ch d (macrocell) 77.76 mhz ch d lvds lpbk (soft ctl) soft ctl soft ctl soft ctl soft ctl soft ctl soft ctl device i/o rx toh processor toh clk quad channel receiver ch a ch b soft ctl ch c ch d soft ctl toh rx b toh rx c toh rx d rx toh frame toh clk tx toh clk en toh tx a toh tx b tx bus a tx bus b toh tx c tx bus c toh tx d tx bus d system frame line frame prot switch a/b data rx bus a data rx bus b prot switch c/d data rx bus c data rx bus d 2 2 2 2 2 2 2 2 lvds out a lvds out b lvds out c lvds out d lvds in a lvds in b lvds in c lvds in d fpga i/f signals cpu interface (async) int_n 8 data 7 addr rd/wr_n cs_n rst_n device i/o or fpga i/f signals (bit stream selectable) soft ctl soft ctl rx toh clk en 622 mhz clks ref fdbk 77.76 mhz 622 mhz 77.76 mhz frame clock toh rx a toh_en system clock (77.76 mhz) 12 12 12 12 9 9 9 9 system clock rx toh clk fpen data rx d en data rx c en data rx b en data rx a en
lattice semiconductor 11 preliminary data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/ ort4622 overview (continued) fpsc conguration con?uration of the ort4622 occurs in two stages, fpga bit stream con?uration and embedded core setup. fpga configuration prior to becoming operational, the fpga goes through a sequence of states, including powerup initialization, con?uration, start-up, and operation. the fpga logic is con?ured by standard fpga bit stream con?ura- tion means as discussed in the series 3 fpga data sheet. additionally, for the ort4622, the location of the cpu interface to the embedded core, either on the device pins or at the fpga/embedded core boundary, is con?ured via fpga con?uration and is de?ed via the ort4622 design kit. the default con?uration sets the cpu interface pins to be active. a simple micropro- cessor emulation soft intellectual property (ip) core that uses very small fpga logic is available from lat- tice. this microprocessor core sets up the embedded core via a state machine and allows the ort4622 to work in an independent system without an external microprocessor interface. embedded core setup the embedded core operation is set up via the embed- ded core cpu interface. all options for the operation of the core are con?ured according to the device register map presented in the detailed description section of this data sheet. during the powerup sequence, the ort4622 device (fpga programmable circuit and the core) is held in reset. all the lvds output buffers and other output buff- ers are held in 3-state. all ?p-?ps in core area are in reset state, with the exception of the boundry scan shift registers, which can only be reset by boundary scan reset. after powerup reset, the fpga can start con?- uration. during fpga con?uration, the ort4622 core will be held in reset and all the local bus interface sig- nals are forced high, but the following active-high sig- nals (prot_switch_a, prot_switch_c, tx_toh_ck_en, sys_fp, line_fp) are forced low. the core_ready signal sent from the embedded core to fpga is held low, indicating core is not ready to interact with fpga logic. at the end of the fpga con- ?uration sequence, the core_ready signal will be held low for six sys_clk cycles after done, tri_io and rst_n (core global reset) are high. then it will go active-high, indicating the embedded core is ready to function and interact with fpga programmable circuit. during fpga recon?uration when done and tri_io are low, the core_ready signal sent from the core to fpga will be held low again to indicate the embedded core is not ready to interact with fpga logic. during fpga partial con?uration, core_ready stays active. the same fpga con?uration sequence described previously will repeat again. the initialization of the embedded core consists of two steps: register con?uration and synchronization of the alignment fifo. in order to con?ure the embedded core, the registers need to be unlocked by writing 0xa0 to address 0x04 and writing 0x01 to address 0x05. control registers 0x04 and 0x05 are lock registers. if the output bus of the data, serial toh port, and toh clock and toh frame pulse are controlled by 3-state registers (the use of the registers for 3-state output control is optional; these output 3-state enable signals are brought across the local bus interface and available to the fpga side), the next step is to activate the 3- state output bus and signals by taking them to func- tional state from high-impedance state. this can be done by writing 0x01 to correspond bits of the channel registers 0x20, 0x38, 0x50, and 0x68. if the 3-state control is done in fpga logic or external logic instead of in the embedded core registers, this step should be done in that particular control logic also. in addition, the synchronization of selected streams is recommended for some networking systems applica- tions. this is a resync of the alignment fifo after the enabled channels have a valid frame pulse. here are the procedures: put all of the streams to be aligned, including disabled streams, into their required align- ment mode. force ais-l in all streams to be synchro- nized (refer to register map, write 0x01 to db1 of register 0x20, 0x38, 0x50, 0x68). wait four frames. write a 0x01 to the fifo alignment resync register, bit db1 of register 0x06. wait four frames. release the ais-l in all streams (write 1 to db1 of register 0x20, 0x38, 0x50, 0x68). this procedures allows normal data ?w through the embedded core.
12 12 lattice semiconductor orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/ generic backplane transceiver application the combination of ort4622 and soft ip cores pro- vides a generic data moving solution for non-sonet applications. there is no requirement for sonet knowledge to the users. all that is needed is to supply the embedded core interface with data, clock, and a 8 khz frame pulse. the provision registers may also need to be set up, and this can be done through either the fpga mpi or in a state machine in the fpga sec- tion (vhdl code available from lattice). the 8 khz frame pulse must be supplied to the sys_fp signal. for generic applications, the frame pulse can be created in fpga logic from the 77.76 mhz sys_clk using a simple resettable counter (the frame pulse should only be high for one cycle of the sys_clk). a vhdl core that automati- cally provides the 8 khz frame pulse is available from lattice. byte-wide data is then sent to each of the transmit channels as follows: the ?st 36 bytes trans- ferred will be invalid data (replaced by overhead), where the ?st byte is sent on the rising edge of sys_clk when sys_fp is high. the next 1044 byte positions can be ?led with valid data. this will repeat a total of nine times (36 invalid bytes followed by 1044 valid bytes) at which time the next 8 khz frame pulse will be found. thus, 87 out of 90 (96.7%) of the data bytes sent are valid user data. on the receive side, an 8 khz pulse must again be sup- plied to sys_fp. in this case, however, only the signal data_rx*_spe must be monitored for each channel, where a high value on this signal means valid data. again 87 out 90 bytes received (96.7%) will be valid data. in order to provide an easy user interface to transfer arbitrary data streams through the ort4622, lattice provides a soft intellectual property (ip) core called the protocol independent framer, or pi-framer. this block transfers user format to the one described above and allows for smoothing/rate transfer of this user data. this framer works with a single channel at 622 mbits/s, two channels at 1.25 gbits/s, or across four channels at 2.5 gbits/s. backplane transceiver core detailed description hsi macro the high-speed interface (hsi) provides a physical medium for high-speed asynchronous serial data trans- fer between the ort4622 and other devices. the devices can be mounted on the same board or mounted on different boards and connected through the shelf backplane. the 622 mbits/s cdr macro is a four-channel clock phase select (cps) and data retime function with serial-to-parallel demultiplexing for the incoming data stream and parallel-to-serial multiplexing for outgoing data. the hsi macro consists of three functionally independent blocks: receiver, transmitter, and pll synthesizer as shown in figure 3. the pll synthesizer block receives a 77.76 mhz refer- ence clock at its input, and provides a phase-locked 622.08 mhz clock to the transmitter block and phase control signal to the receiver block. the pll synthe- sizer block is a common asset shared by four receive and transmit channels. the hsi receiver receives four channels of differential 622.08 mbits/s serial data without clock at its lvds receive inputs. the received data must be scrambled, conforming to sonet sts-12 and sdh stm-4 data formats using either a pn7 or pn9 sequence. the pn7 characteristic polynomial is 1 + x 6 + x 7 , and pn9 char- acteristic polynomial is 1 + x 4 + x 9 . the ort4622 sup- plies a default scrambler using the pn7 sequence. the clock phase select and data retime (cps/dr) module performs a clock recovery and data retiming function by using phase control information. the resultant 622.08 mbits/s data and clock are then passed to the deserializer module, which performs serial-to-parallel conversion and provides a 77.76 mbits/s parallel data and clock at its output. the hsi transmitter receives four channels of 77.76 mbits/s parallel data that is synchronous to the reference clock at its inputs. the serializer performs a parallel-to-serial conversion using a 622.08 mhz clock provided by the pll/synthesizer block. the 622 mbits/s serial data streams are then transmitted through the lvds drivers.
orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 13 lattice semiconductor discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm backplane transceiver core detailed description (continued) 5-8592 (f) figure 3. hsi functional block diagram 622.08 mhz pll synthesizer 50 50 loopbken clock/data alignment phase adjustment demux 622 mbits/s serial to 78 mhz parallel loop- back hsi_rx 622 mbits/s data 622 mhz clock 8 mux 78 mhz parallel to 622 mbits/s serial bs-mux 100 loop- back hdout 622 mbits/s 622.08 mhz clock hsi_tx 622 mbits/s data (77.76 mhz ref clock) ref78 rext (resistor) 622 mbits/s data lvds buffer 8 (77.76 mbytes data) (77.76 mbits/s data) (77.76 mhz clock) 77.76 mhz 77.76 mbytes data bscanen hdin 622 mbits/s lvds buffer select boundary- scan control
lattice semiconductor 14 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm backplane transceiver core detailed description (continued) stm transmitter (fpga -> backplane) the stm has four sts-12 transmit channels which can be treated as a single sts-48 channel. in general, the transmitter circuit receives four byte-wide 77.76 mhz data from the fpga, which nominally represents four sts-12 streams (a, b, c, and d). this data is synchro- nized to the system (reference) clock, and an 8 khz system frame pulse from the fpga logic. transport overhead bytes are then optionally inserted into these streams, and the streams are forwarded to the hsi. all byte timing pulses required to isolate individual over- head bytes (e.g., a1, a2, b1, d1?3, etc.) are gener- ated internally based on the system frame pulse (sys_fp) received from the fpga logic. all streams operate byte-wide at 77.76 mhz in all modes. the toh processor operates from 25 mhz to 77.76 mhz and supports the following toh signals: a1 and a2 inser- tion and optional corruption; h1, h2, and h3 pass transparently; bip-8 parity calculation (after scram- bling) and b1 byte insertion and optional corruption (before scrambling); optional k1 and k2 insert; optional s1/m0 insert; optional e1/f1/e2 insert; optional section data communication channel (dcc, d1?3) and line data communication channel (dcc, d4?12) inser- tion (for intercard communications channel); scram- bling of outgoing data stream with optional scrambler disabling; and optional stream disabling. when the ort4622 is used in nonnetworking applica- tions as a generic high-speed backplane data mover, the toh serial ports are unused or can be used for slow-speed off-channel communication between devices. data received on the parallel bus is optionally scram- bled and transferred to lvds outputs. byte ordering information the core supports quad sts-12 mode of operation on the input/output ports. sts-48 is also supported when received in quad sts-12 format. when operating in quad sts-12 mode, each of the independent byte streams carries an entire sts-12 within it. figure 4 reveals the byte ordering of the individual sts-12 streams and for sts-48 operation. note that the recov- ered data will always continue to be in the same order as transmitted. 5-8574 (f) figure 4. byte ordering of input/output interface in sts-12 mode 12 24 36 48 9 21 33 45 6 18 30 42 3 15 27 39 11 23 35 47 8 20 32 44 5 17 29 41 2 14 26 38 10 22 34 46 7 19 31 43 4 16 28 40 1 13 25 37 1, 12 2, 12 3, 12 4, 12 1, 9 2, 9 3, 9 4, 9 1, 6 2, 6 3, 6 4, 6 1, 3 2, 3 3, 3 4, 3 1, 11 2, 11 3, 11 4, 11 1, 8 2, 8 3, 8 4, 8 1, 5 2, 5 3, 5 4, 5 1, 2 2, 2 3, 2 4, 2 1, 10 2, 10 3, 10 4, 10 1, 7 2, 7 3, 7 4, 7 1, 4 2, 4 3, 4 4, 4 1, 1 2, 1 3, 1 4, 1 sts-12 a sts-12 b sts-12 c sts-12 d sts-12 a sts-12 b sts-12 c sts-12 d sts-48 in quad sts-12 format quad sts-12
lattice semiconductor 15 preliminary data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/ backplane transceiver core detailed description (continued) transport overhead for in band communication the toh byte can be used for in band con?uration, service, and management since it is carried along the same channel as data. in ort4622, in band signaling can be ef?iently utilized, since the total cost of over- head is only 3.3%. transport overhead insertion (serial link) the toh serial links are used to insert toh bytes into the transmit data. the transmit toh data and toh_clk_en get retimed by toh_clk in order to meet setup and hold speci?ations of the device. the retimed toh data is shifted into a 288-bit (36-byte by 8-bit) shift register and then multiplexed as an 8-bit bus to be inserted into the byte-wide data stream. insertion from these serial links or pass-through of toh from the byte-wide data is under software control. transport overhead byte ordering (fpga to backplane) in the transparent mode, spe and toh data received on parallel input bus is transferred, unaltered, to the serial lvds output. however, b1 byte of sts#1 is always replaced with a new calculated value (the 11 bytes following b1 are replaced with all zeros). also, a1 and a2 bytes of all sts-1s are always regenerated. toh serial port in not used in the transparent mode of operation. in the toh insert mode, spe bytes are transferred, unaltered, from the input parallel bus to the serial lvds output. on the other hand, toh bytes are received from the serial input port and are inserted in the sts- 12 frame before being sent to the lvds output. although all toh bytes from the 12 sts-1s are trans- ferred into the device from each serial port, not all of them get inserted in the frame. there are three hard- coded exceptions to the toh byte insertion: framing bytes (a1/a2 of all sts-1s) are not inserted from the serial input bus. instead, they can always be regenerated. parity byte (b1 of sts#1) is not inserted from the serial input bus. instead, it is always recalculated (the 11 bytes following b1 are replaced with all zeros). pointer bytes (h1/h2/h3 of all sts-1s) are not inserted from the serial input bus. instead, they always ?w transparently from parallel input to lvds output. in addition to the above hard-coded exceptions, the source of some toh bytes can be further controlled by software. when con?ured to be in pass-through mode, the speci? bytes must ?w transparently from the parallel input. note that blocks of 12 sts-1 bytes forming an sts-12 are controlled as a whole. there are 15 software controls per channel, as listed below: source of k1 and k2 bytes of the 12 sts-1s (24 bytes) is speci?d by a control bit (per channel control). source of s1 and m0 bytes of the 12 sts-1s (24 bytes) is speci?d by a control bit (per channel control). source of e1, f1, e2 bytes of the sts-1s (36 bytes) is speci?d by a control it (per channel control). source of d1 bytes of the sts-1s (12 bytes) is spec- i?d by a control bit (per channel control). source of d2 bytes of the 12 sts-1s (12 bytes) is speci?d by a control bit (per channel control). source of d3 bytes of the 12 sts-1s (12 bytes) is speci?d by a control bit (per channel control). source of d4 bytes of the 12 sts-1s (12 bytes) is speci?d by a control bit (per channel control). source of d5 bytes of the 12 sts-1s (12 bytes) is speci?d by a control bit (per channel control). source of d6 bytes of the 12 sts-1s (12 bytes) is speci?d by a control bit (per channel control). source of d7 bytes of the 12 sts-1s (12 bytes) is speci?d by a control bit (per channel control). source of d8 bytes of the 12 sts-1s (12 bytes) is speci?d by a control bit (per channel control). source of d9 bytes of the 12 sts-1s (12 bytes) is speci?d by a control bit (per channel control). source of d10 bytes of the 12 sts-1s (12 bytes) is speci?d by a control bit (per channel control). source of d11 bytes of the 12 sts-1s (12 bytes) is speci?d by a control bit (per channel control). source of d12 bytes of the 12 sts-1s (12 bytes) is speci?d by a control bit (per channel control). toh reconstruction is dependent on the transmitter mode of operation. in the transparent mode of opera- tion, toh bytes on lvds output are as shown in table 3.
lattice semiconductor 16 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm backplane transceiver core detailed description (continued) table 3 . transmitter toh on lvds output (transparent mode) in the toh insert mode of operation, toh bytes on lvds output are shown in the following table. this also shows the order in which data is transferred to the serial toh interface, starting with the must signi?ant bit of the ?st a1 byte. the ?st bit of the ?st byte is replaced by an even parity check bit over all toh bytes from the previous toh frame. table 4 . transmitter toh on lvds output (toh insert mode) a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 b1 0 0 0 0 0 0 0 0 0 0 0 regenerated bytes. transparent bytes from parallel input port. a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 b1 0 0 0 0 0 0 0 0 0 0 0 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 f1 f1 f1 f1 f1 f1 f1 f1 f1 f1 f1 f1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 k1 k1 k1 k1 k1 k1 k1 k1 k1 k1 k1 k1 k2 k2 k2 k2 k2 k2 k2 k2 k2 k2 k2 k2 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d8 d8 d8 d8 d8 d8 d8 d8 d8 d8 d8 d8 d9 d9 d9 d9 d9 d9 d9 d9 d9 d9 d9 d9 d10 d10 d10 d10 d10 d10 d10 d10 d10 d10 d10 d10 d11 d11 d11 d11 d11 d11 d11 d11 d11 d11 d11 d11 d12 d12 d12 d12 d12 d12 d12 d12 d12 d12 d12 d12 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 m0 m0 m0 m0 m0 m0 m0 m0 m0 m0 m0 m0 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 regenerated bytes. inserted or transparent bytes. blocks of 12 sts-1 bytes are controlled as a whole. there are 15 controls/channel: k1/k2, s1/m0, e1/f1/e2, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12. transparent bytes (from parallel input port). inserted bytes from toh serial input port.
lattice semiconductor 17 preliminary data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/ backplane transceiver core detailed description (continued) a1/a2 frame insert and testing the a1 and a2 bytes provide a special framing pattern that indicates where a sts-1 begins in a bit stream. all 12 a1 bytes of each sts-12 are set to 0xf6, and all 12 a2 bytes of the sts-12 are set to 0x28 when not over- ridden with an user-speci?d value for testing. a1/a2 testing (corruption) is controlled per stream by the a1/a2 error insert register. when a1/a2 corruption detection is set for a particular stream, the a1/a2 val- ues in the corrupted a1/a2 value registers are sent for the number of frames de?ed in the corrupted a1/a2 frame count register. when the corrupted a1/a2 frame count register is set to zero, a1/a2 corruption will con- tinue until the a1/a2 error insert register is cleared. on a per-device basis, the a1 and a2 byte values are set, as well as the number of frames of corruption. then, to insert the speci?d a1/a2 values, each chan- nel has an enable register. when the enable register is set, the a1/a2 values are corrupted for the number speci?d in the number of frames to corrupt. to insert errors again, the per-channel fault insert register must be cleared, and set again. only the last a1 and the ?st a2 are corrupted. b1 calculation and insertion a bit interleaved parity ? (bip-8) error check set for even parity over all the bits of an sts-1 frame. b1 is de?ed for the ?st sts-1 in an sts-n only. the b1 calculation block computes a bip-8 code, using even parity over all bits of the previous sts-12 frame after scrambling and is inserted in the b1 byte of the current sts-12 frame before scrambling. per-bit b1 corruption is controlled by the force bip-8 corruption register (reg- ister address 0f). for any bit set in this register, the corresponding bit in the calculated bip-8 is inverted before insertion into the b1 byte position. each stream has an independent fault insert register that enables the inversion of the b1 bytes. b1 bytes in all other sts- 1s in the stream are ?led with zeros. stream disable when disabled via the appropriate bit in the stream enable register, the prescrambled data for a stream is set to all ones, feeding the hsi. the hsi macro is pow- ered down on a per-stream basis, as are its lvds out- puts. scrambler the data stream is scrambled using a frame synchro- nous scrambler of sequence length 127. the scram- bling function can be disabled by software. the generating polynomial for the scrambler is 1 + x 6 + x 7 . this polynomial conforms to the standard sonet sts-12 data format. the scrambler is reset to 1111111 on the ?st byte of the spe (byte following the z0 byte in the twelfth sts-1). that byte and all subsequent bytes to be scrambled are exclusive-ored, with the output from the byte-wise scrambler. the scrambler runs continuously from that byte on throughout the remainder of the frame. a1, a2, j0, and z0 bytes are not scrambled. system frame pulse and line frame pulse system frame pulse (for transmitter) and line frame pulse (for receiver) are generated in fpga logic. a1/a2 framing is used on the link for locating the 8 khz frame location. all frames sent to the fpga are aligned to the fpga frame pulse line_fp which is provided by the fpga to the stm macro. all frames sent from the fpga to the stm will be aligned to the frame pulse sys_fp that is supplied to the stm macro. in either directions, system frame pulse and line frame pulse are active for one system clock cycle, indicating the loca- tion of a1 byte of sts#1. they are common to all four channels.
18 18 lattice semiconductor orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/ backplane transceiver core detailed description (continued) stm receiver (backplane -> fpga) the ort4622 has four receiving channels that can be treated as one sts-48 stream, or treated as indepen- dent channels. incoming data is received through lvds serial ports at the data rate of 622 mbits/s. the receiver can handle the data streams with frame off- sets of up to ?2 bytes which would be due to timing skews between cards and along backplane traces. the received data streams are processed in the hsi and the stm, and then passed through the cic boundary to the fpga logic. framer block the framer block, in figure 5, takes byte-wide data from the hsi, and outputs a byte-aligned, byte-wide data stream and 8 khz sync pulse. the framer algo- rithm determines the out-of-frame/in-frame status of the incoming data and will cause interrupts on both an errored frame and an out-of-frame (oof) state. the framer detects the a1/a2 framing pattern and gener- ates the 8 khz frame pulse. when the framer detects oof, it will generate an interrupt. also, the framer detects an errored frame and increments an a1/a2 frame error counter. the counter can be monitored by a processor to compile performance status on the quality of the backplane. because the ort4622 is intended for use between it and another ort4622 or other devices via a back- plane, there is only one errored frame state. thus after two transitions are missed, the state machine goes into the oof state and there is no severely errored frame (sef) or loss-of-frame (lof) indication. b1 calculate and descramble (backplane -> fpga) each rx block receives byte-wide scrambled 77.76 mhz data and a frame sync from the framer. since each hsi is independently clocked, the rx block operates on individual streams. timing signals required to locate overhead bytes to be extracted are generated internally based on the frame sync. the rx block pro- duces byte-wide (optionally) descrambled data and an output frame sync for the alignment fifo block. the b1 calculation block computes a bip-8 (bit inter- leaved parity 8-bits) code, using even parity over all bits of the previous sts-12 frame before descrambling; this value is checked against the b1 byte of the current frame after descrambling. a per-stream b1 error counter is incremented for each bit that is in error. the error counter may be read via the cpu interface. descrambling. the streams are descrambled using a frame synchronous descrambler of sequence length 127 with a generating polynomial of 1 + x 6 + x 7 . the a1/a2 framing bytes, the section trace byte (j0) and the growth bytes (z0) are not descrambled. the descrambling function can be disabled by software. ais-l insertion. alarm indication signal (ais) is a con- tinuous stream of unframed 1s sent to alert down- stream equipment that the near-end terminal has failed, lost its signal source, or has been temporarily taken out of service. if enabled in the ais_l force regis- ter, ais-l is inserted into the received frame by writing all ones for all bytes of the descrambled stream. ais-l insertion on out-of-frame. if enabled via a register, ais-l is inserted into the received frame by writing all ones for all bytes of the descrambled stream when the framer indicates that an out-of-frame condi- tion exists. internal parity generation even parity is generated on all data bytes and is routed in parallel with the data to be checked before the pro- tection switch mux at the parallel output. fifo alignment (backplane -> fpga) the alignment fifo allows the transfer of all data to the system clock. the fifo sync block (figure 5) allows the system to be con?ured to allow the frame alignment of multiple slightly varying data streams. this optional alignment ensures that matching sts-12 streams will arrive at the fpga end in perfect data sync. the frame alignment is con?urable to allow for the possibility of fully independent (i.e., total frame mis- alignment) sts-12s.
lattice semiconductor 19 preliminary data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/ backplane transceiver core detailed description (continued) 5-8577 (f) figure 5. interconnect of streams for fifo alignment the incoming data from the clock and data recovery can be separated into four sts-12 channels (a, b, c, and d). these streams can be frame aligned in the pat- terns shown in figure 6. 5-8575 (f) figure 6. alignment of four sts-12 streams there is also a provision to allow certain streams to be disabled (i.e., not producing interrupts or affecting syn- chronization). these streams can be enabled at a later time without disrupting other streams. the fifo block consists of a 24 by 10-bit fifo per link. this fifo is used to align up to ?54.3 ns of interlink skew and to transfer to the system clock. the fifo sync circuit takes metastable hardened frame pulses from the write control blocks and produces sync signals that indicate when the read control blocks should begin reading from the ?st fifo location. on top of the sync signals, this block produces an error indicator which indicates that the signals to be aligned are too far apart for alignment (i.e., greater than 18 clocks apart). sync and error signals are sent to read control block for alignment. the read control block is synched only once on start-up; any further synchronization is software controlled. the action of resynching a read control block will always cause loss of data. a register allows the read control block to be resynched. link alignment. the general operation of the link alignment algorithm is to wait 12 clocks (i.e., half the fifo) from the arriving frame pulse and then signal the read control block to begin reading. for perfectly aligned frame pulses across the links, it is simply a matter of counting down 12 and then signaling the read control block. the algorithm down counts by one until all of the frame pulses have arrived and then by two when they are all present. for example (figure 7), if all pulses arrive together, then alignment algorithm would count 24 (12 clocks); if, however, the arriving pulses are spread out over four clocks, then it would count one for the ?st four pulses and then two per clock afterward, which gives a total of 14 clocks between ?st frame pulse and the ?st read. this puts the center of arriving frame pulses at the halfway point in the buffer. this is the extent of the algorithm, and it has no facility for actively correcting problems once they occur. the write control block receives byte-wide data at 77.76 mhz and a frame pulse two clocks before the ?st a1 byte of the sts-12 frame. it generates the write address for the fifo block. the ?st a1 in every sts- 12 stream is written in the same location (address 0) in the fifo. also, a frame bit is passed through the fifo along with the ?st byte before the ?st a1 of the sts- 12. the read control block synchronizes the reading of the fifo for streams that are to be aligned. reading begins when the fifo sync signals that all of the appli- cable a1s and the appropriate margin have been writ- ten to the fifo. all of the read blocks to be synchronized begin reading at the same time and same location in memory (address 0). the alignment algorithm takes the difference between read address and write address to indicate the relative clock alignments between sts-12 streams. if this depth indication exceeds certain limits (12 clocks), then an interrupt is given to the microprocessor (alignment over?w). each sts-12 stream can be realigned by software if it gets too far out of line (this would cause a loss of data). for background applications that have less than 154.3 ns of interlink skew, misalignment will not occur. sts-12 stream a sts-12 stream b sts-12 stream c sts-12 stream d fifo sync stream a stream b stream c stream d stream a stream b stream c stream d
lattice semiconductor 20 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm backplane transceiver core detailed description (continued) 5-8584 (f) figure 7. examples of link alignment pointer mover block (backplane -> fpga) the pointer mover maps incoming frames to the line framing that is supplied by the fpga logic. the k1/k2 bytes and h1-ss bits are also passed through to the pointer generator so that the fpga can receive them. the pointer mover handles both concatenations inside the sts-12, and to other sts-12s inside the core. the pointer mover block can correctly process any length of concatenation of sts frames (multiple of three) as long as it begins on an sts-3 boundary (i.e., sts-1 number one, four, seven, ten, etc.) and is contained within the smaller of sts-3, 12, or 48. see details in table 5. table 5 . valid starting positions for an sts-mc sts-1 number sts-3cspe sts-6cspe sts-9cspe sts-12cspe sts-15cspe sts-18c to sts-48c spes 1 yes yes yes yes yes yes 4 yes yes yes no yes 7 yes yes no no yes 10 yes no no no yes 13 yes yes yes yes yes 16 yes yes yes no yes 19 yes yes no no yes 22 yes no no no yes 25 yes yes yes yes yes 28 yes yes yes no yes 31 yes yes no no yes 34 yes no no no yes no 37 yes yes yes yes no no 40 yes yes yes no no no 43 yes yes no no no no 46 yes no no no no no note: yes = sts-mc spe can start in that sts-1. no = sts-mc spe cannot start in that sts-1. ?= yes or no, depending on the particular value of m. 24-byte fifo 24-byte fifo all fps 12 clocks sync. pulse arrive together (writing begins) (reading begins) sync. pulse (reading begins) last fp arrives 4 clocks first fp arrives (writing begins) 10 clocks perfectly aligned frames 4-byte spread in arriving frames
lattice semiconductor 21 preliminary data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/ backplane transceiver core detailed description (continued) pointer interpreter state machine. the pointer inter- preters highest priority is to maintain accurate data ?w (i.e., valid spe only) into the elastic store. this will ensure that any errors in the pointer value will be cor- rected by a standard, fully sonet compliant, pointer interpreter without any data hits. this means that error checking for increment, decrement, and new data ?g (ndf) (i.e., eight of 10) is maintained in order to ensure accurate data ?w. a single valid pointer (i.e., 0?82) that differs from the current pointer will be ignored. two consecutive incoming valid pointers that differ from the current pointer will cause a reset of the j1 location to the latest pointer value (the generator will then produce an ndf). this block is designed to handle single bit errors without affecting data ?w or changing state. the pointer interpreter has only three states (norm, ais, and conc). norm state will begin whenever two consecutive norm pointers are received. if two con- secutive norm pointers are received that both differ from the current offset, then the current offset will be reset to the last received norm pointer. when the pointer interpreter changes its offset, it causes the pointer generator to receive a j1 value in a new posi- tion. when the pointer generator gets an unexpected j1, it resets its offset value to the new location and declares an ndf. the interpreter is only looking for two consecutive pointers that are different from the current value. these two consecutive norm pointers do not have to have the same value. for example, if the cur- rent pointer is ten and a norm pointer with offset of 15 and a second norm pointer with offset of 25 are received, then the interpreter will change the current pointer to 25. the receipt of two consecutive conc pointers causes conc state to be entered. once in this state, offset values from the head of the concate- nation chain are used to determine the location of the sts spe for each sts in the chain. two consecutive ais pointers cause the ais state to occur. any two con- secutive normal or concatenation pointers will end this ais state. this state will cause the data leaving the pointer generator to be overwritten with 0xff. 5-8589 (f) figure 8. pointer mover state machine pointer generator. the pointer generator maps the corresponding bytes into their appropriate location in the outgoing byte stream. the generator also creates offset pointers based on the location of the j1 byte as indicated by the pointer interpreter. the generator will signal ndfs when the interpreter signals that it is com- ing out of ais state. the pointer generator resets the pointer value and generates ndf every time a byte marked j1 is read from the elastic store that doesn? match the previous offset. increment and decrement signals from the pointer interpreter are latched once per frame on either the f1 or e2 byte times (depending on collisions); this ensures constant values during the h1 through h3 times. the choice of which byte time to do the latching on is made once when the relative frame phases (i.e., received and system) are determined. this latch point is then stable unless the relative framing changes and the received h byte times collide with the system f1 or e2 times, in which case the latch point would be switched to the col- lision-free byte time. there is no restriction on how many or how often incre- ments and decrements are processed. any received increment or decrement is immediately passed to the generator for implementation regardless of when the last pointer adjustment was made. the responsibility for meeting the sonet criteria for maximum frequency of pointer adjustments is left to an upstream pointer processor. when the interpreter signals an ais state, the genera- tor will immediately begin sending out 0xff in place of data and h1, h2, h3. this will continue until the inter- preter returns to norm or conc (pointer mover state machine) states and a j1 byte is received. norm conc ais 2 x conc 2 x norm 2 x norm 2 x ais 2 x conc 2 x ais
lattice semiconductor 22 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm backplane transceiver core detailed description (continued) transport overhead extraction transport overhead is extracted from the receive data stream by the toh extract block. the incoming data gets loaded into a 36-byte shift register on the system clock domain. this, in turn, is clocked onto the toh clock domain at the start of the spe time, where it can be clocked out. during the spe time, the receiver toh frame pulse is generated, rx_toh_fp, which indicates the start of the row of 36 toh bytes. this pulse, along with the receive toh clock enable, rx_toh_ck_en, as well as the toh data, are all launched on the rising edge of the toh clock toh_clk. toh byte ordering (backplane to fpga) the toh processor is responsible for dropping all toh bytes of each channel through one of four correspond- ing serial ports. the four toh serial ports are synchro- nized to the toh clock (the same clock that is being used by the serial ports on the transmitter side). this free-running toh clock is provided to the core by external circuitry and operates at a minimum frequency of 25 mhz and a maximum frequency of 77.76 mhz. data is transferred over serial links in a bursty fashion as controlled by the rx toh clock enable signal, which is generated by the asic and common to the four channels. all toh bytes of sts-12 streams are trans- ferred over the appropriate serial link in the same order in which they appear in a standard sts-12 frame. data transfer should be preformed on a row-by-row basis such that internal data buffering needs is kept to a min- imum. data transfers on the serial links will be synchro- nized relative to the rx toh frame signal. receiver toh reconstruction receiver toh reconstruction on output parallel bus is as shown in the following table. table 6 . receiver toh (output parallel bus) on the toh serial port, all toh bytes are dropped as received on the lvds input (msb ?st). the only exception is the most signi?ant bit of byte a1 of sts#1, which is replaced with an even parity bit. this parity bit is calculated over the previous toh frame. also, on ais-l (either resulting from lof or forced through software), all toh bits are forced to all ones with proper parity (parity we automatically ends up being set to 1 on ais-l). special toh byte functions k1 and k2 handling. the k1 and k2 bytes are used in automatic protection switch (aps) applications. k1 and k2 bytes can be optionally passed through the pointer mover under software control, or can be set to zero with the other toh bytes. a1 and a2 handling. as discussed previously, the a1 and a2 bytes are used for a framing header. a1 and a2 bytes are always regenerated and set to hexadecimal f6 and 28, respectively. a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 000000000000 k100000000000 k200000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 regenerated bytes. regenerated bytes (under pointer generator control-ss bits must be transparent-ais-p must be supported). bytes taken from elastic store buffer, on negative stuff opportunity-else, forced to all zeros. transparent or all zeros (k1/k2 are either taken from k1/k2 buffer or forced to all zeros-soft, control). in transparent mode, ais-l must be supported. all zero bytes.
orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 23 lattice semiconductor discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm backplane transceiver core detailed description (continued) spe and c1j1 outputs . these two signals for each channel are passed to the fpga logic to allow a pointer pro- cessor or other function to extract payload without interpreting the pointers. for the ort4622, each frame has 12 sts-1s. in the spe region, there are 12 j1 pulses for each sts-1s. there is one c1(j0, new sonet speci?a- tions use j0 instead of c1 as section trace to identify each sts-1 in an sts-n) pulse in the toh area for one frame. thus, there is a total of 12 j1 pulses and one c1(j0) pulse per frame. c1(j0) pulse is coincident with the j0 of sts1 #1. in each frame, the spe ?g is active when the data stream is in spe area. spe behavior is dependent on pointer movement and concatenation. note that in the toh area, h3 can also carry valid data. when valid spe data is carried in this h3 slot, spe is high in this particular toh time slot. in the spe region, if there is no valid data during any spe column, the spe signal will be set to low. spe allow a pointer processor to extract payload without interpreting the pointers. the spe and c1j1 functionality are described in table 7. for generic data operation, valid data is available when spe is 1 and the c1j1 signal is ignored. table 7 . spe and c1j1 functionality note: the following rules are observed for generating spe and c1j1 signals: on occurrence of ais-p on any of the sts-1, there i s no corre- sponding j1 pulse. in case of concatenated payloads (up to sts48c), only the head sts-1 of the group has an associated j1 pulse . c1j1 signal tracks any pointer movements. during a negative justi?ation event, spe is set high during the h3 byte to indicate that pay- load data is available. during a positive justi?ation event, spe is set low during the positive stuff opportunity byte to indi cate that payload data is not available. 5-9330(f) notes: c1j1 signal behavior shown in this ?ure is just for illustration purposes: c1 pulse position must always be as shown; ho wever, position of j1 pulses vary based on path overhead location of each sts-1 within the sts-12 stream. c1j1 signal must always be active during c1(j0) time slot of sts#1. c1j1 signal must also be active during the twelve j1 time slots. however, c1j1 must not be active for any sts-1 for which ais-p is gen- erated. also, on concatenated payloads, only the head of the group must have a j1 pulse. figure 9. spe and c1j1 functionality spe c1j1 description 0 0 toh information excluding c1(j0) of sts1 #1. 0 1 position of c1(j0) of sts1 #1 (one per frame). typically used to provide a unique link identi?ation (256 possible unique links) to help ensure cards are connected into the backplane correctly or cables are connected correctly. 1 0 spe information excluding the 12 j1 bytes. 1 1 position of the 12 j1 bytes. sts-12 toh row # 1 spe row # 1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 j0 z0 z0 z0 z0 z0 z0 z0 z0 z0 z0 z0 sts-12 spe c1j1 c1 pulse j1 pulse of 3rd sts-1 1st spe bytes of the 12 sts-1s 123456789101112
lattice semiconductor 24 preliminary data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm backplane transceiver core detailed description (continued) 5-9331 notes: spe signal behavior shown in this ?ure is just for illustration purposes: spe behavior is dependent on pointer movements and concate- nation. spe signal must be high during negative stuff opportunity byte time slots (h3) for which valid data is carried (negative stuf? g). spe signal must be low during positive stuff opportunity byte time slots for which there is no valid data (positive stuf?g). figure 10. spe stuff bytes sts-12 toh row # 4 spe row # 4 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 sts-12 spe positive stuff opportunity bytes 123456789101112 negative stuff opportunity bytes spe signal shows negative stuffing for 2nd sts-1, and positive stuffing for 6th sts-1 powerdown mode powerdown mode will be entered when the corre- sponding channel is disabled. channels can be inde- pendently enabled or disabled under software control. parallel data bus output enable and toh serial data output enable signals are made available to the fpga logic. the hsi macrocells corresponding channel is also powered down. the device will power up with all four channels in powerdown mode. in addition, an lvds_en pin has been added to control the lvds pins during boundary scan. during functional operation, enabling/disabling lvds buffers is controlled by software registers. when in boundary scan mode, lvds_en controls the enabling/disabling of lvds buff- ers instead of software registers. this lvds_en pin should be pulled high on the board for functional opera- tion, and pulled low during boundary scan. redundancy and protection switching the ort4622 supports sts-12/sts-48 redundancy by either software or hardware control for protection switching applications. for the transmitter mode, no additional functionality is required for redundant opera- tion. for receiving data, sts-12 data redundancy can be implemented within the same device, while sts-48 and above data stream requires a pair of ort4622 devices to support redundancy. in sts-12 mode, the channel a receive data bus port is used for both channel a and channel b. similarly, the channel c receive data bus port is used for both chan- nel c and channel d. channel b and channel d become the redundant channels. the channel b and channel d receive data bus ports are unused. soft reg- isters provide independent control to the protection switching muxes for both parallel data ports and serial toh data ports. when direct hardware control for pro- tection switching is needed, external protection switch pins are available for channels a and b, and also chan- nels c and d. the external protection switch pins only support parallel spe/toh data protection switching, but not the serial toh data. in sts-48 mode, two independent devices are required to work and protect for redundancy. parallel and serial port output pins on the fpga side should be 3-stated as the basis for supporting redundancy. the existing local bus enable signals at the cic can be used as 3- state controls for fpga data bus if needed, which can be easily accessed by software control. users can also create their own protection switch 3-state enable sig- nals either in fpga logic or external to the device, depending on the speci? application.
orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 25 lattice semiconductor discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm memory map de?ition of register types there are six structural register elements: sreg, creg, preg, iareg, isreg, and iereg. there are no mixed registers in the chip. this means that all bits of a particular register (particular address) are structurally the same. table 8 . structural register elements registers access and general description the memory map comprises three address blocks: generic register block: id, revision, scratch pad, lock, fifo alignment, and reset registers. device register block: control and status bits, common to the four channels. channel register blocks: each of the four channels have an address block. the four address blocks have the exact same structure with a constant address offset between channel register blocks. all registers are write-protected by the lock register, except for the scratch pad register. the lock register is a 16-bit read/write register. write access is given to registers only when the key value 0xa001 is present in the lock register. an error ?g will be set upon detecting a write access when write permission is denied. the default value is 0x0000. after powerup reset or soft reset, unused register bits will be read as zeros. unused address locations are also read as zeros. write only register bits will be read as zeros. the detailed information on register access and func- tion are described on the tables, memory map, and memory map bit description. element register description sreg status register a status register is read only, and, as the name implies, is used to convey the status information of a particular element or function of the ort4622 core. the reset value of an sreg is really the reset value of the particular element or function that is being read. in some cases, an sreg is really a ?ed value. an example of which is the ?ed id and revision registers. creg control register a control register is read and writable memory element inside core control. the value of a creg will always be the value written to it. events inside the ort4622 core cannot effect creg value. the only exception is a soft reset, in which case the creg will return to its default value. the control register have default values as de?ed in the default value column of table 9. preg pulse register each element, or bit, of a pulse register is a control or event signal that is asserted and then deasserted when a value of one is written to it. this means that each bit is always of value 0 until it is written to, upon which it is pulsed to the value of one and then returned to a value of 0. a pulse register will always have a read value of 0. iareg interrupt alarm register each bit of an interrupt alarm register is an event latch. when a particular event is produced in the ort4622 core, its occurrence is latched by its associated iareg bit. to clear a particular iareg bit, a value of one must be written to it. in the ort4622 core, all isreg reset values are 0. isreg interrupt status register each bit of an interrupt status register is physically the logical-or function. it is a consolidation of lower level interrupt alarms and/or isreg bits from other registers. a direct result of the fact that each bit of the isreg is a logical-or function means that it will have a read value of one if any of the consolidation signals are of value one, and will be of value 0 if and only if all consolidation signals are of value 0. in the ort4622 core, all isreg default values are 0. ereg interrupt enable register each bit of a status register or alarm register has an associated enable bit. if this bit is set to value one, then the event is allowed to propagate to the next higher level of consolidation. if this bit is set to zero, then the associated iareg or isreg bit can still be asserted but an alarm will not propagate to the next higher level. an interrupt enable bit is an interrupt mask bit when it is set to value 0.
lattice semiconductor 26 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm memory map (continued) memory map overview table 9 . memory map notes: 1.generic register block. 2.device register block-rx. 3.device register block-tx. addr [6:0] reg. type db7 db6 db5 db4 db3 db2 db1 db0 default value (hex) notes generic register block 00 sreg ?ed rev [7:0] 01 1 01 sreg ?ed id lsb [7:0] 01 02 sreg ?ed id msb [7:0] a0 03 creg scratch pad [7:0] 00 04 creg lockreg msb [7:0] 00 05 creg lockreg lsb [7:0] 00 06 preg fifo align- ment com- mand global reset command na device register block 08 creg rx toh frame and rx toh clock enable control ext prot sw en ext prot sw function sts-48 sts-12 sel (unused in ort4622) lvds lpbk control 00 2 09 creg parallel port out- put mux select for ch c parallel port out- put mux select for ch a serial port output mux select for ch c serial port output mux select for ch a 0f 0a creg fifo aligner threshold value (min) [4:0] 02 0b creg fifo aligner threshold value (max) [4:0] 15 0c creg scrambler/ descram- bler control input/ output parallel bus par- ity control line loop- back control number of consecutive a1/a2 errors to generate [3:0] 60 3 0d creg a1 error insert value [7:0] 00 0e creg a2 error insert value [7:0] 00 0f creg transmitter b1 error insert mask [7:0] 00
orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 27 lattice semiconductor discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm memory map (continued) table 9 . memory map notes: 1.generic register block. 2.device register block-rx. 3.device register block-tx. 4.top-level interrupts. 5.rx control. 6.tx control signals. 7.per sts#1 cos ?g. * addr values delimited by a comma indicate the address for each of four channels, from channel a to d. for example, the registe r to tx con- trol signals has addresses of 20, 38, 50, and 68. this indicates that channel a tx control signals are at address 20, control b tx control sig- nals are at address addr [6:0] reg. type db7 db6 db5 db4 db3 db2 db1 db0 default value (hex) notes device register block (continued) 10 isreg per device int ch d interrupt ch c interrupt ch b interrupt ch a interrupt 00 4 11 iereg enable/mask register [4:0] 00 12 iareg write to locked register error ?g frame offset error ?g 00 13 iereg enable/mask register [1:0] 00 channel register block 20, 38, 50, 68 * creg protec- tion switching 3-state control of toh data output protec- tion switching 3-state control of parallel data out- put channel enable/ disable control parallel output bus par- ity err ins cmd rx k1/k2 source select toh serial output port par err ins cmd force ais-l control rx behavior in lof 01 5 21, 39, 51, 69 creg tx mode of opera- tion tx e1 f1 e2 source select tx s1 m0 source select tx k1/k2 source select tx d12 source select tx d11 source select tx d10 source select tx d9 source select 00 6 22, 3a, 52, 6a creg tx d8 source select tx d7 source select tx d6 source select tx d5 source select tx d4 source select tx d3 source select tx d2 source select tx d1 source select 00 23, 3b, 53, 6b creg b1 error insert command a1/a2 error ins command 00 24, 3c, 54, 6c sreg concatin- dication 12 concatin- dication 9 concatin- dication 6 concatin- dication 3 na 7 25, 3d, 55, 6d sreg concatin- dication 11 concatin- dication 8 concatin- dication 5 concatin- dication 2 concatin- dication 10 concatin- dication 7 concatin- dication 4 concatin- dication 1 na
lattice semiconductor 28 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm memory map (continued) table 9 . memory map notes: 1. generic register block. 2. device register block-rx. 3. device register block-tx. 4. top-level interrupts. 5. rx control. 6. tx control signals. 7. per sts#1 cos ?g. 8. per channel interrupt. 9. per sts-12 interrupt ?gs. 10. per sts-1interrupt ?gs. addr [6:0] reg. type db7 db6 db5 db4 db3 db2 db1 db0 default value (hex) notes channel register block (continued) 26, 3e, 56, 6e isreg elastic store overow ?g ais-p ?g per sts-12 alarm ?g 00 8 27, 3f, 57, 6f iereg enable/mask register [2:0] 00 28, 40, 58, 70 iareg toh serial input port parity error ?g input parallel bus parity error ?g lvds link b1 parity error ?g lof ?g receiver internal path parity error ?g fifo aligner threshold error ?g 00 9 29,41, 59, 71 iereg enable/mask register [5:0] 00 2a, 42, 5a, 72 iareg ais interrupt ?gs 12 ais interrupt ?g 9 ais interrupt ?g 6 ais interrupt ?gs 3 00 10 2b, 43, 5b, 73 iareg ais interrupt ?g 11 ais interrupt ?g 8 ais interrupt ?g 5 ais interrupt ?g 2 ais interrupt ?g 10 ais interrupt ?g 7 ais interrupt ?g 4 ais interrupt ?g 1 00 2c, 44, 5c, 74 iereg enable/ mask ais interrupt ?g 12 enable/ mask ais interrupt ?g 9 enable/ mask ais interrupt ?g 6 enable/ mask ais interrupt ?g 3 00 2d, 45, 5d, 75 iereg enable/ mask ais interrupt ?g 11 enable/ mask ais interrupt ?g 8 enable/ mask ais interrupt ?g 5 enable/ mask ais interrupt ?g 2 enable/ mask ais interrupt ?g 10 enable/ mask ais interrupt ?g 7 enable/ mask ais interrupt ?g 4 enable/ mask ais interrupt ?g 1 00 2e, 46, 5e, 76 iareg es overow ?g 12 es overow ?g 9 es overow ?g 6 es overow ?g 3 00
29 29 lattice semiconductor orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm memory map (continued) table 9 . memory map notes: 1. generic register block. 2. device register block-rx. 3. device register block-tx. 4. top-level interrupts. 5. rx control. 6. tx control signals. 7. per sts#1 cos ?g. 8. per channel interrupt. 9. per sts-12 interrupt ?gs. 10. per sts-1interrupt ?gs. 11. binning. addr [6:0] reg. type db7 db6 db5 db4 db3 db2 db1 db0 default value (hex) notes channel register block (continued) 2f, 47, 5f, 77 iareg es overow ?g 11 es overow ?g 8 es overow ?g 5 es overow ?g 2 es overow ?g 10 es overow ?g 7 es overow ?g 4 es overow ?g 1 00 10 30, 48, 60, 78 iereg enable/ mask es overow ?gs 12 enable/ mask es overow ?g 9 enable/ mask es overow ?gs 6 enable/ mask es overow ?gs 3 00 31, 49, 61, 79 iereg enable/ mask es overow ?g 11 enable/ mask es overow ?g 8 enable/ mask es overow ?g 5 enable/ mask es overow ?g 2 enable/ mask es overow ?g 10 enable/ mask es overow ?g 7 enable/ mask es overow ?g 4 enable/ mask es overow ?g 1 00 32, 4a, 62, 7a counter over?w lvds link b1 parity error counter 00 11 33, 4b, 63, 7b counter over?w lof counter 00 34, 4c, 64, 7c counter over?w a1/a2 frame error counter 00
lattice semiconductor 30 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm memory map (continued) table 10 . memory map bit descriptions bit/register name(s ) bit/ register location (hex) register type default value (hex) description generic register block ?ed rev [7:0] ?ed id lsb [7:0] ?ed id msb [7:0] 00 [7:0] 01 [7:0] 02 [7:0] sreg 01 01 a0 scratch pad [7:0] 03 [7:0] creg 00 the scratch pad has no function and is not used anywhere in the ort4622 core. however, this register can be written to and read from. lockreg msb [7:0] lockreg lsb [7:0] 04 [7:0] 05 [7:0] creg 00 00 in order to write to registers in memory locations 06 to 7f, lockreg msb and lockreg lsb must be respectively set to the values of a0 and 01. if the msb and lsb lockreg values are not set to {a0, 01}, then any values written to the registers in memory locations 06 to 7f will be ignored. after reset (both hard and soft), the ort4622 core is in a write locked mode. the ort4622 core needs to be unlocked before it can be written to. also note that the scratch pad register (03) can always be written to since it is unaffected by write lock mode. fifo alignment command global reset command 06 [0] 06 [1] preg na the fifo alignment and global reset commands are both accessed via the pulse register in memory address 06. the fifo alignment command is used to frame align the outputs of the four receive stm stream fifos. the global reset command is a soft (software initiated) reset. neverthe- less, the global reset command will have the exact reset effect as a hard (rst_n pin) reset. device register block lvds loopback con- trol 08 [0] creg 0 0 no loopback. 1 lvds loopback, transmit to receive on. sts48 sts12 sel 08 [1] creg 0 this control signal is untracked in the ort4622 core. it is a scratch bit, and its value has no effect on the ort4622 core. ext prot sw en ext prot sw func 08 [3:2] creg 0 ext prot sw en ext prot sw func switching control master. 0 mux is controlled by software (one control bit per mux). output buffer 3-state signals are controlled by software (one control bit per channel). 1 0 mux on parallel output bus of channel a is controlled by prot_switch a/b pin (0-> channel a, 1-> channel b). mux on parallel output bus of channel c is controlled by prot_switch c/d pin (0 -> channel c, 1-> channel d). output buffer 3-state signals are controlled by software (one control bit per channel). 1 1 mux is controlled by software (one control bit per mux). output buffer 3-state signals on parallel output bus of chan- nels a and b are controlled by prot_switch a/b pin (0-> buffers active, 1-> hi-z). output buffer 3-state signals on parallel output bus of chan- nels c and d are controlled by prot_switch c/d pin (0 -> buffers active, 1-> hi-z).
orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 31 lattice semiconductor discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm memory map (continued) table 10. memory map bit descriptions bit/register name(s ) bit/ register location (hex) register type default value (hex) description device register block (continued) rx toh frame and rx toh clock enable 08 [4] creg 0 0 toh_ck_fp_en = 0, can be used to 3-state rx_toh_ck_en and rx_toh_fp signals. 1 functional mode. serial output port a mux select serial output port a mux select parallel output port a mux select parallel output port a mux select 09 [0] 09 [1] 09 [2] 09 [3] creg 1 1 1 1 toh output mux select for port a 0 toh output port a is multiplexed to channel b. 1 toh output port a is multiplexed to channel a. toh output mux select for port c 0 toh output port c is multiplexed to channel d. 1 toh output port c is multiplexed to channel c. parallel port output mux select for port a 0 parallel output data bus port a is multiplexed to channel b. 1 parallel output data bus port a is multiplexed to channel a. parallel port output mux select for port c 0 parallel output data bus port c is multiplexed to channel d. 1 parallel output data bus port c is multiplexed to channel c. fifo aligner thresh- old value (min) [4:0] fifo aligner thresh- old value (max) [4:0] 0a [4:0] 0b [4:0] creg 02 15 these are the minimum and maximum thresholds values for the per channel receive direction alignment fifos. if and when the minimum or maximum threshold value is violated by a particular channel, then the interrupt event fifo aligner threshold error will be generated for that channel and latched as a fifo aligner threshold error ?g in the respective per sts-12 interrupt alarm register. the allowable range for minimum threshold values is 0 to 23. the allowable range for maximum threshold values is 0 to 22. note that the minimal and maximum fifo aligner threshold values apply to all four channels. number of consecu- tive a1/a2 errors to generate [3:0] a1 error insert value [7:0] a2 error insert value [7:0] 0c [3:0] 0d [7:0] 0e [7:0] creg 00 00 00 these three-per-device control signals are used in conjunction with the per-channel a1/a2 error insert command control bits to force a1/a2 errors in the transmit direction. if a particular channels a1/a2 error insert command control bit is set to the value one, then the a1 and a2 error insert values will be inserted into that channels respective a1 and a2 bytes. the number of consecu- tive frames to be corrupted is determined by the number of consecutive a1, a2 errors to generate[3:0] control bits. the error insertion is based on a rising edge detector. as such, the con- trol must be set to value 0 before trying to initiate a second a1/a2 cor- ruption. line loopback control 0c [4] creg 0 0 no loopback. 1 receive to transmit loopback on fpga side. input/output parallel bus parity control 0c [5] creg 0 0 even parity. 1 odd parity.
lattice semiconductor 32 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm memory map (continued) table 10. memory map bit descriptions bit/register name(s ) bit/ register location (hex) register type default value (hex) description device register block (continued) scrambler/ descrambler control 0c [6] creg 1 0 no receive direction descramble/transmit direction scramble. 1 in receive direction, descramble channel after sonet frame recovery. in transmit direction scramble data just before paral- lel-to-serial conversion. transmit b1 error insert mask [7:0] 0f [7:0] creg 00 0 no error insertion. 1 invert corresponding bit in b1 byte. channel a int channel b int channel c int channel d int per device int enable/mask register [4:0] 10 [0] 10 [1] 10 [2] 10 [3] 10 [4] 11 [4:0] creg creg creg creg creg iereg 0 0 0 0 0 0 consolidation interrupts 0 no interrupt. mask interrupt in enable/mask register. 1 interrupt. enable interrupt in enable/mask register. frame offset error ?g write to locked register error ?g enable/mask register [1:0] 12 [0] 12 [1] 13 [1:0] iareg iareg iereg 0 0 0 if in the receive direction the phase offset between any two channels exceeds 17 bytes, then a frame offset error event will be issued. this condition is continuously moni- tored. if the ort4622 core memory map has not been unlocked (by writing a1 00 to the lock registers), and any address other than the lockreg registers or scratch pad register is written to, then a write to locked register event will be gen- erated. channel register block (channel a, channel b, channel c, channel d) rx behavior in lof 20, 38 50, 68 [0] 1 receive behavior in lof 0 when receive direction oof occurs, do not insert ais-l. 1 when receive direction oof occurs, insert ais-l. force ais-l control 20, 38, 50, 68 [1] 0 force ais-l control 0 do not force ais-l. 1 force ais-l. toh serial output port par err ins cmd 20, 38, 50, 68 [2] 0 0 do not insert a parity error. 1 insert parity error in parity bit of receive toh serial output for as long as this bit is set. rx k1/k2 source select 20, 38, 50, 68 [3] 0 0 set receive direction k1/k2 bytes to 0. 1 pass receive direction k1/k2 though pointer mover. parallel output bus par- ity err ins cmd 20, 38, 50, 68 [4] 0 0 do not insert parity error. 1 insert parity error in the parity bit of receive direction parallel output bus for as long as this bit is set.
orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 33 lattice semiconductor discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm memory map (continued) table 10. memory map bit descriptions * the error insertion is based on a rising edge detector. as such, the control must be set to value 0 before trying to initiate a second a1/a2 corruption. ? the error insertion is based on a rising edge detector. as such, the control must be set to value 0 before trying to initiate a second b1 corruption. bit/register name(s ) bit/ register location (hex) register type default value (hex) description channel register block (channel a, channel b, channel c, channel d) (continued) channel enable/disable control 20, 38, 50, 68 [5] creg 0 channel enable/disable control 0 powerdown channel a/b/c/d cdr and lvds i/o can be used with data_rx_en to 3-state output buses. 1 functional mode. hi-z control of parallel output bus. 20, 38, 50, 68 [6] creg 0 to be used as 3-state control for pro- tection switching on the fpga data output. hi-z control of toh data output. 20 [7] creg 0 to be used as 3-state control for toh data output. only channel a enable sig- nal is brought out. tx mode of operation 21, 39, 51, 69 [7] creg 0 transmit mode of operation 0 insert toh from serial ports. 1 pass through all toh. tx e1 f2 e2 source select tx s1 m0 source select tx k1 k2 source select tx d12?9 source select tx d8?1 source select 21, 39, 51, 69 [6] 21, 39, 51, 69 [5] 21, 39, 51, 69 [4] 21, 39, 51, 69 [3:0] 22, 3a, 52, 6a [7:0] creg creg creg creg creg 0 0 0 4?0 8?00 other registers 0 insert toh from serial ports. 1 pass through that particular toh byte. a1/a2 error insert command 23, 3b, 53, 6b [0] creg 0 0 do not insert error.* 1 insert error for number of frames in register hex 0c.* b1 error insert command 23, 3b, 53, 6b [1] creg 0 0 do not insert error. ? 1 insert error for one frame in b1 bits de?ed by register hex 0f. ? concatindication 12, 9, 6, 3 concatindication 11, 8, 5, 2, 10, 7, 4, 1 24, 3c, 54, 6c [3:0] 25, 3d, 55, 6d [7:0] sreg sreg 0 0 the value one in any bit location indi- cates that sts# is in concat mode. a 0 indicates that the sts is not in concat mode, or is the head of a concat group. per sts-12 alarm ?g ais-p ?g elastic store over?w ?g enable/mask register [2:0] 26, 3e, 56, 6e [0] 26, 3e, 56, 6e [1] 26, 3e, 56, 6e [2] 27, 3f, 57, 6f [2:0] isreg isreg isreg iereg 0 0 0 3?000 these ?g register bits per sts-12 alarm ?g, ais-p ?g, and elastic store over?w ?g are the per-channel inter- rupt status (consolidation) register. fifo aligner threshold error flag receiver internal path parity error flag lof flag lvds link b1 parity error flag input parallel bus parity error flag toh serial input port parity error flag enable/mask register [5:0] 28, 40, 58, 70 [0] 28, 40, 58, 70 [1] 28, 40, 58, 70 [2] 28, 40, 58, 70 [3] 28, 40, 58, 70 [4] 28, 40, 58, 70 [5] 29, 41, 59, 71 [5:0] iareg iareg iareg iareg iareg iareg iareg 0 0 0 0 0 0 6?00 these are per the sts-12 alarm flags with the corresponding enable/mask register. ais interrupt flags 12, 9, 6, 3 ais interrupt flags 11, 8, 5, 2, 10, 7, 4, 1 enable/mask register 12, 9, 6, 3 enable/mask register 11, 8, 5, 2, 10, 7, 4, 1 2a, 42, 5a, 72 [3:0] 2b, 43, 5b, 73 [7:0] 2c, 44, 5c, 74 [3:0] 2d, 45, 5d, 75 [7:0] iareg iareg iereg iereg 4?0 8?00 4?0 8?00 these are the ais-p alarm flags with the corresponding enable/mask register.
lattice semiconductor 34 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm memory map (continued) table 10. memory map bit descriptions * the error insertion is based on a rising edge detector. as such, the control must be set to value 0 before trying to initiate a second a1/a2 corruption. ? the error insertion is based on a rising edge detector. as such, the control must be set to value 0 before trying to initiate a second b1 corruption. powerup sequencing for ort4622 device orca series ort4622 device uses two power supplies: one to power the device i/os and the asic core (v dd ), which is set to 3.3 v for 3.3 v operation and 5 v tolerance on input pins, and another supply for the internal fpga logic (v dd 2), which is set to 2.5 v. it is understood that many users will derive the 2.5 v core logic supply from a 3.3 v power supply, so the following recommendations are made for the powerup sequence of the supplies and allow- able delays between power supplies reaching stable voltages. in general, both the 3.3 v and the 2.5 v supplies should ramp-up and become stable as close together in time as possible. there is no delay requirement if the v dd 2 (2.5 v) supply becomes stable prior to the v dd (3.3 v) supply. there is a delay requirement imposed if the v dd sup- ply becomes stable prior to the v dd 2 supply. the requirement is that the v dd 2 (2.5 v) supply transition from 0 v to 2.3 v within 15.7 ms if the v dd (3.3 v) supply is already stable at a minimum of 3.0 v. if the v dd supply has not yet reached 3.0 v when the v dd 2 supply has reached 2.3 v, then the requirement is that the v dd 2 supply reach a minimum of 2.3 v within 15.7 ms of when the v dd supply reaches 3.0 v. if the chosen power supplies cannot meet this delay requirement, it is always possible to hold off con?uration of the fpga by asserting init or prgm until the v dd 2 supply has reached 2.3 v. this process eliminates any power supply sequencing issues. bit/register name(s ) bit/ register location (hex) register type default value (hex) description channel register block (channel a, channel b, channel c, channel d) (continued) es overflow flags 12, 9, 6, 3 es overflow flags 11, 8, 5, 2, 10, 7, 4, 1 enable/mask register 12, 9, 6, 3 enable/mask register 11, 8, 5, 2, 10, 7, 4, 1 2e, 46, 5e, 76 [7:0] 2f, 47, 5f, 77 [3:0] 30, 48, 60, 78 [7:0] 31, 49, 61, 79 [7:0] 4?0 8?00 4?0 8?00 these are the elastic store overflow alarm flags. lvds link b1 parity error counter 32, 4a, 62, 7a [7:0] counter 8?00 7-bit count + overflow-reset on read. lof counter 33, 4b, 63, 7b [7:0] counter 8?00 7-bit count + overflow-reset on read. a1/a2 frame error counter 34, 4c, 64, 7c [7:0] counter 8?00 7-bit count + overflow-reset on read.
lattice semiconductor 35 preliminary data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/ fpga configuration data format the isplever development system interfaces with front-end design entry tools and provides tools to pro- duce a fully con?ured fpsc. this section discusses using the isplever development system to generate con?uration ram data and then provides the details of the con?uration frame format. using isplever to generate conguration ram data the con?uration data bit stream de?es the embed- ded core con?uration, the fpga logic functionality, and the i/o con?uration and interconnection. the data bit stream is generated by the isplever development tools. the bit stream created by the bit stream genera- tion tool is a series of 1s and 0s used to write the fpsc con?uration ram. it can be loaded into the fpsc using one of the con?uration modes discussed else- where in this data sheet. for fpscs, the bit stream is prepared in two separate steps in the design ?w. the con?uration options of the embedded core are speci?d using orca ort4622 design kit software at the beginning of the design process. this offers the designer a speci? con- ?uration to simulate and design the fpga logic to. upon completion of the design, the bit stream genera- tor combines the embedded core options and the fpga con?uration into a single bit stream for down- load into the fpsc. fpga conguration data frame con?uration data can be presented to the fpsc in two frame formats: autoincrement and explicit. a detailed description of the frame formats is shown in figure 11, figure 12, and table 11. the two modes are similar except that autoincrement mode uses assumed address incrementation to reduce the bit stream size, and explicit mode requires an address for each data frame. in both cases, the header frame begins with a series of 1s and a preamble of 0010, followed by a 24-bit length count ?ld representing the total number of con?uration clocks needed to complete the loading of the fpsc. the mandatory id frame contains data used to deter- mine if the bit stream is being loaded to the correct type of orca device (i.e., a bit stream generated for an ort4622 is being sent to an ort4622). error check- ing is always enabled for series 3+ devices, through the use of an 8-bit checksum. one bit in the id frame also selects between the autoincrement and explicit address modes for this load of the con?uration data. a con?uration data frame follows the id frame. a data frame starts with a one-start bit pair and ends with enough one-stop bits to reach a byte boundary. if using autoincrement con?uration mode, subsequent data frames can follow. if using explicit mode, one or more address frames must follow each data frame, telling the fpsc at what addresses the preceding data frame is to be stored (each data frame can be sent to multiple addresses). following all data and address frames is the postam- ble. the format of the postamble is the same as an address frame with the highest possible address value with the checksum set to all ones.
lattice semiconductor 36 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm fpga con?uration data format (continued) figure 11. serial configuration data format autoincrement mode figure 12. serial configuration data format explicit mode note: for slave parallel mode, the byte containing the preamble must be 11110010. the number of leading header dummy bits must be (n * 8) + 4, where n is any nonnegative integer and the number of trailing dummy bits must be (n * 8), where n is any positive integer. the number of stop bits/frame for slave parallel mode must be (x * 8), where x is a positive integer. note also that the bit stream generator tool supplies a bit stream that is compatible with all con?uration modes, including slave parallel mode. table 11. con?uration frame format and contents header 11110010 preamble. 24-bit length count con?uration frame length. 11111111 trailing header? bits. id frame 0101 1111 1111 1111 id frame header. con?uration mode 00 = autoincrement, 01 = explicit. reserved [41:0] reserved bits set to 0. id 20-bit part id. checksum 8-bit checksum. 11111111 eight stop bits (high) to separate frames. configuration data frame (repeated for each data frame) 01 data frame header. data bits number of data bits depends upon device. alignment bits = 0 string of 0 bits added to bit stream to make frame header, plus data bits reach a byte boundary. checksum 8-bit checksum. 11111111 eight stop bits (high) to separate frames. configuration address frame 00 address frame header. 14 address bits 14-bit address of location to start data storage. checksum 8-bit checksum. 11111111 eight stop bits (high) to separate frames. postamble 00 postamble header. 11111111 111111 dummy address. 1111111111111111 16 stop bits. 5-5759(f) configuration data configuration data 10 01 01 preamble length id frame configuration configuration postamble configuration header 00 00 count data frame 1 data frame 2 5-5760(f) preamble length id frame configuration configuration postamble configuration header address address 00 count data frame 1 data frame 2 frame 2 frame 1 configuration data configuration data 10 01 01 00 00 00
lattice semiconductor 37 preliminary data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/ fpga con?uration data format (continued) bit stream error checking there are three different types of bit stream error checking performed in the orca series 3+ fpscs: id frame, frame alignment, and crc checking. the id data frame is sent to a dedicated location in the fpsc. this id frame contains a unique code for the device for which it was generated. this device code is compared to the internal code of the fpsc. any differ- ences are ?gged as an id error. this frame is auto- matically created by the bit stream generation program in isplever. each data and address frame in the fpsc begins with a frame start pair of bits and ends with eight stop bits set to 1. if any of the previous stop bits were a 0 when a frame start pair is encountered, it is ?gged as a frame alignment error. error checking is also done on the fpsc for each frame by means of a checksum byte. if an error is found on evaluation of the checksum byte, then a checksum/parity error is ?gged. when any of the three possible errors occur, the fpsc is forced into an idle state, forcing init low. the fpsc will remain in this state until either the reset or prgm pins are asserted. if using either of the mpi modes to con?ure the fpsc, the speci? type of bit stream error is written to one of the mpi registers by the fpga con?uration logic. the pgrm bit of the mpi control register can also be used to reset out of the error condition and restart con?ura- tion. fpga con?uration modes there are eight methods for con?uring the fpsc. six of the con?uration modes are selected on the m0, m1, and m2 input and are shown in table 12. a fourth input, m3, is used to select the frequency of the internal oscil- lator, which is the source for cclk in some con?ura- tion modes. the nominal frequencies of the internal oscillator are 1.25 mhz and 10 mhz. the 1.25 mhz fre- quency is selected when the m3 input is unconnected or driven to a high state. note that the master parallel mode of con?uration that is available in the orca series 3 fpgas is not avail- able in the ort4622. more information on the general fpga modes of con- ?uration can be found in the orca series 3 data sheet. table 12. con?uration modes * motorola is a registered trademark of motorola, inc. ? intel is a registered trademark of intel corporation. m2 m1 m0 cclk configuration mode data 0 0 0 output master serial serial 0 0 1 input slave parallel parallel 0 1 0 output microprocessor: motorola * pow- erpc parallel 0 1 1 output microprocessor: intel ? i960 parallel 1 0 0 reserved 1 0 1 output async peripheral parallel 1 1 0 reserved 1 1 1 input slave serial serial
lattice semiconductor 38 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. the orca series 3+ fpscs include circuitry designed to protect the chips from damaging substrate injection cur- rents and to prevent accumulations of static charge. nevertheless, conventional precautions should be observed during storage, handling, and use to avoid exposure to excessive electrical stress. table 13 . absolute maximum ratings recommend operating conditions table 14 . recommend operating conditions parameter symbol min max unit storage temperature t stg ?5 150 ? i/o supply voltage with respect to ground v dd 4.2 v internal supply voltage v dd 2 3.2 input signal with respect to ground cmos i/o 5 v tolerant i/o ?.5 ?.5 v dd + 0.3 5.8 v v signal applied to high-impedance output ?.5 v dd + 0.3 v maximum package body temperature 220 ? junction temperature t j ?0 125 ? ort4622 temperature range (ambient) i/o supply voltage (v dd ) internal supply voltage (v dd 2) 0 ? to 70 ? 3.3 v 5% 2.5 v 5%
orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 39 lattice semiconductor discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm electrical characteristics table 15 . general electrical characteristics ort4622 commercial: v dd = 3.3 v 5%, v dd 2 = 2.5 v 5%, 0 ? < t a < 70 ? . table 16 . electrical characteristics for fpga i/o ort4622 commercial: v dd = 3.3 v 5%, v dd 2 = 2.5 v 5%, 0 ? < t a < 70 ? . * the pull-up resistor will externally pull the pin to a level 1.0 v below v dd . symbol parameter test conditions ort4622 unit min max i ddsb standby current (t a = 25 ?, v dd = 3.3 v, v dd 2 = 2.5 v) internal oscillator running, no output loads, inputs at v dd or gnd (after conguration) 5.3 ma i ddsb standby current (t a = 25 ?, v dd = 3.3 v, v dd 2 = 2.5 v) internal oscillator stopped, no output loads, inputs at v dd or gnd (after con?uration) 1.4 ma v dr data retention voltage t a = 25 ? 2.3 v i pp powerup current power supply current at approximately 1 v, within a recom- mended power supply ramp rate of 1 ms?00 ms 2.7 ma parameter symbol test conditions ort4622 unit min max input voltage: high low v ih v il input con?ured as cmos (clamped to v dd ) 50% v dd gnd ?0.5 v dd + 0.3 30% v dd v v input voltage: high low v ih v il input con?ured as 5 v tolerant 50% v dd gnd ?0.5 5.8 30% v dd v v output voltage: high low v oh v ol v dd = min, i oh = 6 ma or 3 ma v dd = min, i ol = 12 ma or 6 ma 2.4 0.4 v v input leakage current i l v dd = max, v in = v ss or v dd ?0 10 ? input capacitance c in (t a = 25 ?, v dd = 3.3 v, v dd 2 = 2.5 v) test frequency = 1 mhz ?pf output capacitance c out (t a = 25 ?, v dd = 3.3 v, v dd 2 = 2.5 v) test frequency = 1 mhz ?pf done pull-up resistor* r done 100 k m[3:0] pull-up resistors* r m 100 k i/o pad static pull-up current* i pu (v dd = 3.6 v, v in = v ss , t a = 0 ?) 14.4 50.9 ? i/o pad static pull-down current i pd (v dd = 3.6 v, v in = v ss, t a = 0 ?) 26 103 ? i/o pad pull-up resistor* r pu v dd = all, v in = v ss , t a = 0 ? 100 k i/o pad pull-down resistor r pd v dd = all, v in = v dd , t a = 0 ? 50 k
lattice semiconductor 40 preliminary data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm electrical characteristics (continued) table 17 . electrical characteristics for embedded core i/o other than lvds i/o note: all outputs are driving 35 pf, except cpu data bus pins which drive 100 pf. it is assumed that the ttl buffers from the standard-cell library can handle the 100 pf load. symbol parameter min max unit v ih input high voltage (ttl input) 2.0 5.5 v v il input low voltages (ttl input) 0.8 v v oh output high voltage (ttl output) 2.4 v v oh output low voltage (ttl output) 0.4 v hsi circuit specifications input data the 622 mbits/s scrambled input data stream must conform to sonet sts-12 and sdh stm-4 data for- mat using either a pn7 or pn9 sequence. the pn7 characteristic is 1 + x 6 + x 7 and the pn9 characteristic is 1 + x 4 + x 9 . the ort4622 supplies a default scram- bler using the pn7 sequence. the longest allowable stream of nontransitional 622 mbits/s input data is 60 bits. this sequence should not occur more often than once per minute. an input signal phase change of no more than 100 ps is allowed over 200 ns time interval, which translates to a frequency change of 500 ppm. the signal eye opening must be greater than 0.4 uip-p (unit interval peak-to-peak), and the unit interval for 622 mbits/s is 1.6075 ns. jitter tolerance the input jitter tolerance of the ort4622 is shown in table 18. table 18 . jitter tolerance generated output jitter the generated output jitter is a maximum of 0.2 uip-p from 250 khz to 5 mhz. pll pll requires an external 10 k pull-down resistor. table 19 . pll input reference clock table 20 . input reference clock frequency uip-p 250 khz 0.6 25 khz 6.0 2 khz 60 parameter min max unit loop bandwidth 6 mhz jitter peaking 2 db powerup reset duration 10 s lock acquisition 1 ms parameter min max frequency deviation 20 ppm frequency change 500 ppm phase change in 200 ns 100 ps
orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 41 lattice semiconductor discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm hsi circuit specifications (continued) power supply decoupling lc circuit the 622 mhz hsi macro contains both analog and digital circuitry. the data recovery function, for example, is implemented as primarily a digital function, but it relies on a conventional analog phase-locked loop to provide its 622 mhz reference frequency. the internal analog phase-locked loop contains a voltage-controlled oscillator. this circuit will be sensitive to digital noise generated from the rapid switching transients associated with internal logic gates and parasitic inductive elements. generated noise that contains frequency components beyond the band- width of the internal phase-locked loop (about 3 mhz) will not be attenuated by the phase-locked loop and will impact bit error rate directly. thus, separate power supply pins are provided for these critical analog circuit ele- ments. additional power supply ?tering in the form of a lc pi ?ter section will be used between the power supply source and these device pins as shown in figure 13. the corner frequency of the lc ?ter is chosen based on the power supply switching frequency, which is between 100 khz and 300 khz in most applications. capacitors c1 and c2 are large electrolytic capacitors to provide the basic cutoff frequency of the lc ?ter. for example, the cutoff frequency of the combination of these elements might fall between 5 khz and 50 khz. capaci- tor c3 is a smaller ceramic capacitor designed to provide a low-impedance path for a wide range of high-frequency signals at the analog power supply pins of the device. the physical location of capacitor c3 must be as close to the device lead as possible. multiple instances of capacitors c3 can be used if necessary. the recommended ?ter for the hsi macro is shown below: l = 4.7 h, rl = 1 , c1 = 0.01 f, c2 = 0.01 f, c3 = 4.7 f. 5-9344(f) figure 13. sample power supply filter network for analog hsi power supply pins c2 + c3 + to device pll_vdda pll_vssa c1 + from power supply source l
lattice semiconductor 42 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm l vds i/o table 21. lvds driver dc data* * external reference, ref10 = 1.0 v ?3%, ref14 = 1.4 v ?3% table 22 . lvds driver ac data parameter symbol test conditions min typ max unit driver output voltage high, v oa or v ob v oh r load = 100 ?1% 1.475* v driver output voltage low, v oa or v ob v ol r load = 100 ?1% 0.925* v driver output differential voltage v od = (v oa ?v ob ) (with external reference resistor) v od r load = 100 ?1% 0.25 0.45* v driver output offset voltage v os = (v oa + v ob )/2 v os r load = 100 ?1% 1.125* 1.275* v output impedance, single ended r o v cm = 1.0 v and 1.4 v 40 50 60 r o mismatch between a and b delta r o v cm = 1.0 v and 1.4 v 10 % change in |v od | between 0 and 1 r load = 100 ?1% 25 mv change in |v os | between 0 and 1 r load = 100 ?1% 25 mv output current i sa, i sb driver shorted to ground 24ma output current i sab drivers shorted together 12ma power-off output leakage |xa|, |xb| v dd = 0 v v pa d , v padn = 0 v? v 30 ? parameter symbol test conditions min max unit v od fall time, 80% to 20% t fall z load = 100 ?1% c pa d = 3 pf, c pad = 3 pf 100 200 ps v od rise time, 20% to 80% t rise z load = 100 ?1% c pad = 3 pf, c pad = 3 pf 100 200 ps differential skew |tphla ?tplhb| or |tphlb ?tplha| t skew1 any differential pair on package at 50% point of the transition ?0ps channel-to-channel skew |tpdiffm ?tpdiffn|, t skew2 any two signals on package at 0 v differential ps propagation delay time t plh t phl z load = 100 w ?1% c pa d = 3 pf, c padn = 3 pf 0.50 0.55 0.90 1.03 ps
orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 43 lattice semiconductor discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm lvds i/o (continued) lvds receiver buffer requirements table 23 . lvds receiver dc data * buffer will not produce output transition when input is open-circuited. note: v dd = 3.1 v?.5 v, 0 ? ?25 ? , slow-fast process. table 24 . lvds receiver ac data table 25 . lvds receiver power consumption table 26. lvds operating parameters note: under worst-case operating condition, the lvds driver will withstand a disabled or unpowered receiver for an unlimited period of time without being damaged. similarly, when outputs are short-circuited to each other or to ground, the lvds will not suffer permanent damage. the lvds driver supports hot-insertion. under a well-controlled environment, the lvds i/o can drive backplane as well as cable. parameter symbol test conditions min typ max unit receiver input voltage range, v ia or v ib v i |v gpd | < 925 mvdc 1 mhz 0 1.2 2.4 v receiver input differential threshold |v idth ||v gpd | < 925 mv 400 mhz ?00 100 mv receiver input differential hysteresis v hyst v idthh ?v idthl *mv receiver differential input impedance r in with built-in termination, center-tapped 80 100 120 symbol parameter test conditions min max unit t pwd receiver output pulse-width distortion |v idth | = 100 mv 311 mhz tbd ps t plh , t phl propagation delay time c l = 1.5 pf 0.75 0.74 1.65 1.82 ns with common-mode variation, (0 v to 2.4 v) c l = 1.5 pf 50 ps t rise receiver output signal rise time, v od 20% to 80% c l = 1.5 pf 150 350 ps t fall receiver output signal fall time, v od 80% to 20% c l = 1.5 pf 150 350 ps symbol parameter test conditions min max unit pr dc receiver dc power dc 34.8 mw pr ac receiver ac power ac, c l = 1.5 pf 0.026 mw/mhz parameter test conditions min normal max unit transmit termination resistor 100 receiver termination resistor 50 temperature range ?0 125 ?c power supply v dd 3.1 3.5 v power supply v ss 0v
44 44 lattice semiconductor orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/ timing characteristics description the most accurate timing characteristics are reported by the timing analyzer in the isplever development system. a timing report provided by the development system after layout divides path delays into logic and routing delays. the timing analyzer can also provide logic delays prior to layout. while this allows routing budget estimates, there is wide variance in routing delays associated with different layouts. the logic timing parameters noted in the electrical characteristics section of this data sheet are the same as those in the design tools. in the pfu timing, symbol names are generally a concatenation of the pfu oper- ating mode and the parameter type. the setup, hold, and propagation delay parameters, de?ed below, are designated in the symbol name by the set, hld, and del characters, respectively. the values given for the parameters are the same as those used during production testing and speed bin- ning of the devices. the junction temperature and sup- ply voltage used to characterize the devices are listed in the delay tables. actual delays at nominal tempera- ture and voltage for best-case processes can be much better than the values given. it should be noted that the junction temperature used in the tables is generally 85 ?. the junction temperature for the fpga depends on the power dissipated by the device, the package thermal characteristics ( ja ), and the ambient temperature, as calculated in the following equation and as discussed further in the package thermal characteristics summary section: t jmax = t amax + (p ? ja ) ? note : the user must determine this junction tempera- ture to see if the delays from isplever should be derated based on the following derating tables. table 27 and table 28 provide approximate power sup- ply and junction temperature derating for or3lp26b commercial devices. the delay values in this data sheet and reported by isplever are shown as 1.00 in the tables. the method for determining the maximum junction temperature is de?ed in the package thermal characteristics section. taken cumulatively, the range of parameter values for best-case vs. worst-case pro- cessing, supply voltage, and junction temperature can approach three to one. table 27. derating for commercial devices (i/o supply v dd ) table 28. derating for commercial devices (i/o supply v dd 2) note: the derating tables shown above are for a typical critical path that contains 33% logic delay and 66% routing delay. since the routing delay derates at a higher rate than the logic delay, paths with more than 66% routing delay will derate at a higher rate than shown in the table. the approximate derating values vs. temperature are 0.26% per ? for logic delay and 0.45% per ? for routing delay. the approximate derating values vs. voltage are 0.13% per mv for both logic and routing delays at 25 ?. t j (?) power supply voltage 3.0 v 3.3 v 3.6 v ?0 0.82 0.72 0.66 0 0.91 0.80 0.72 25 0.98 0.85 0.77 85 1.00 0.99 0.90 100 1.23 1.07 0.94 125 1.34 1.15 1.01 t j (?) power supply voltage 2.38 v 2.5 v 2.63 v ?0 0.86 0.71 0.67 0 0.94 0.79 0.73 25 0.99 0.84 0.77 85 1.00 0.99 0.92 100 1.23 1.05 0.96 125 1.33 1.13 1.03
lattice semiconductor 45 preliminary data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/ timing characteristics (continued) propagation delay ?he time between the speci?d reference points. the delays provided are the worst- case of the tphh and tpll delays for noninverting func- tions, tplh and tphl for inverting functions, and tphz and tplz for 3-state enable. setup time ?he interval immediately preceding the transition of a clock or latch enable signal, during which the data must be stable to ensure it is recognized as the intended value. hold time ?he interval immediately following the transition of a clock or latch enable signal, during which the data must be held stable to ensure it is recognized as the intended value. 3-state enable ?he time from when a 3-state control signal becomes active and the output pad reaches the high-impedance state. pfu timing refer to orca series 3 data sheet for the following: combination pfu timing characteristics sequential pfu timing characteristics ripple mode pfu timing characteristics synchronous memory write characteristics synchronous memory read characteristics plc timing refer to orca series 3 data sheet for the following: pfu output mux and direct routing timing charac- teristics slic timing refer to orca series 3 data sheet for the following: supplemental logic and interconnect cell (slic) tim- ing characteristics pio timing refer to orca series 3 data sheet for the following: programmable i/o (pio) timing characteristics special function timing refer to orca series 3 data sheet for the following: microprocessor interface (mpi) timing characteristics programmable clock manager (pcm) timing charac- teristics boundary-scan timing characteristics clock timing refer to orca series 3 data sheet for the following: expressclk (eclk) and fast clock (fclk) timing characteristics general-purpose clock timing characteristics (inter- nally generated clock) ort4622 expressclk to output delay (pin-to-pin) ort4622 fast clock (fclk) to output delay (pin-to- pin) ort4622 general system clock (sclk) to output delay (pin-to-pin) ort4622 input to expressclk (eclk) fast capture setup/hold time (pin-to-pin) ort4622 input to fast clock setup/hold time (pin-to- pin) ort4622 input to general system clock setup/hold time (pin-to-pin) con?uration timing refer to orca series 3 data sheet for con?uration timing characteristics. readback timing refer to orca series 3 data sheet for readback tim- ing characteristics.
lattice semiconductor 46 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm timing characteristics (continued) table 29. ort4622 embedded core and fpga interface clock operation frequencies ort4622 commercial: v dd = 3.3 v 5%, v dd 2 = 2.5 v 5%, 0 ? < t a < 70 ?. * the sys_clk clock frequency is based on the hsi macro speci?ations. all embedded core/fpga on-chip interface timing is available in isplever through the stamp timing ?e included in the ort4622 design kit. description (t i = 85 ?, v dd = min, v dd 2 = min) speed ? unit signal min typ max sys_clk 0 * 77.76* mhz toh_clk 0 25 77.76 mhz
orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 47 lattice semiconductor discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm timing characteristics (continued) clock timing 5-8605 (f) figure 14. transmit parallel port timing (backplane -> fpga) table 30 . timing requirements (transmit parallel port timing) symbol parameter min nom max unit t p clock period 12.86 ns t l clock low time 5.1 6.43 7.7 ns t h clock high time 5.1 6.43 7.7 ns t l t p t h first a1 of sts1 #1 fpga_sysclk sys_fp data_tx bus (data bus from fpga to embedded core)
lattice semiconductor 48 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm timing characteristics (continued) 5-8606 figure 15. transmit transport delay (fpga -> backplane) table 31 . timing requirements (transmit transport delay) symbol parameter min nom max unit t prop number of clocks of delay from parallel bus input to lvds output 4 7 8 sys_clk t prop a1 of sts1 #1 sys_clk sys_fp data_tx bus (parallel data from fpga to embedded core) hdout (lvds data out) first a1 of sts1 #1
orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 49 lattice semiconductor discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm timing characteristics (continued) 5-8607 (f) figure 16. receive parallel port timing ( backplane -> fpga) table 32 . timing requirements (receive parallel port timing) symbol parameter min nom max unit t p clock period 12.86 ns t l clock low time 5.1 6.43 7.7 ns t h clock high time 5.1 6.43 7.7 ns t l t p t h sys_clk line_fp data_rx bus (from embedded core to fpga) first a1 of sts1 #1 parity, spe, c1j1 pins
lattice semiconductor 50 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm timing characteristics (continued) 5-8608 (f) * data bus refers to 8 bits data, 1 bit parity, 1 bit spe, and 1 bit c1j1. ? channel a or c refers to whether the prot_sw_a or prot_sw_c pins that are activated. for example, if the prot_sw_a pin is activated, the timing diagram for output bus a or c refers to output bus a. figure 17. protection switch timing table 33 . timing requirements (protection switch timing) symbol parameter min nom max unit t tr transport delay from latching of prot_sw_a/c to actual data switch 7 8 9 leading edge sys_clks t hiz transport delay from latching of prot_sw_a/c to actual hi-z 4 5 6 leading edge sys_clks t ch propagation delay from sys_clk to hi-z of output bus 25 leading edge sys_clks sys_clk prot_sw_a ... or prot_sw_c ... ... ... data_rx bus* a or c sys_clk data_rx bus ? a & b or c & d ch a/c ch a/c ch a/c ch a/c ch b/d t tr t hiz t ch ch a & b/ ch c & d ch a & b/ ch c & d ch a & b/ ch c & d ch a & b/ ch c & d
orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 51 lattice semiconductor discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm timing characteristics (continued) 5-8609 (f) figure 18. toh input serial port timing (fpga -> backplane) table 34 . timing requirements (toh input serial port timing) symbol parameter min nom max unit t p clock period 12.86 40 ns t hi clock high time 5.1 6.43 7.7 ns t lo clock low time 5.1 6.43 7.7 ns sys_clk sys_fp ... ... ... ... data_tx bus toh_clk 1044 bytes spe ... ... tx toh_ (parallel bus) toh serial input clk_ena row #1 row #9 36 bytes toh 1044 bytes spe 36 bytes toh guard band (4 toh clk) guard band (4 toh clk) msbit(7) of b1 byte sts1 #1 bit 6 of b1 byte sts1 #1 t p t hi t lo
lattice semiconductor 52 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm timing characteristics (continued) 5-8610 (f) note: the total delay from a1 sts1 #1 arriving at lvds input to rx_toh_fp is 56 sys_clks and 6 toh_clks. this will vary by ?4 sys_clks, 12 each way for the fifo alignment, and ? sys_clks due to the variability in the clock recovery of the hsi macro. figure 19. toh output serial port timing (backplane -> fpga) table 35 . timing requirements (toh output serial port timing) symbol parameter min nom max unit t trans_sys delay from first a1 lvds serial input to transfer to toh_clk 44 56 68 sys_clks t trans_toh delay from transfer to toh_clk to rx_toh_fp 6 toh_clks rx toh fp hdin toh_clk 1044 bytes spe rx toh (input lvds serial 622m data) toh serial output clk ena row #1 row #9 36 bytes toh 1044 bytes spe 36 bytes toh msbit(7) of a1 byte sts #1 bit 6 of a1 byte sts #1 t trans_sys t trans_toh bit 0 of a1 byte sts #1 ... ... ... ... ...
orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 53 lattice semiconductor discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm timing characteristics (continued) 5-8611 (f) note: the cpu interface can be bit stream selected either from device i/o or fpga interface. the timing diagram applies to both interfaces, but not to the fpga mpi block. figure 20. cpu write transaction table 36 . timing requirements (cpu write transaction) symbol parameter min max unit t pulse minimum pulse width for cs_n 5 ns t addr_max maximum time from negative edge of cs_n to addr valid ?8ns t dat_max maximum time from negative edge of cs_n to data valid ?5ns t rd_wr_max maximum time from negative edge of cs_n to negative edge of rd_wr_n ?6ns t write_max maximum time from negative edge of cs_n to contents of internal register latching db[7:0] 60 ns t access_min minimum time between a write cycle (falling edge of cs_n) and any other transaction (read or write at falling edge of cs_n) 60 ns t int_max maximum time from register ff to pad 20 ns t rw_wr_n, addr, db_hold minimum hold time that rd_wr_n, addr and db must be held valid from the negative edge of cs_n 57 ns data valid t access_min t pulse old value new value t write_max t int_max t addr_max t dat_max rd_wr_max cpu_cs_n cpu_rd_wr_n cpu_addr[6:0] cpu_data[7:0] internal register (sys_clk domain) cpu_int_n t rd_wr_n, addr_max, db_hold (cs_n) (rd_wr_n) (addr[6:0]) (db[7:0]) (int_n)
lattice semiconductor 54 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm timing characteristics (continued) 5-8612 (f) notes: the cpu interface can be bit stream selected either from device i/o or fpga interface. the timing diagram applies to both inter faces, but not to the fpga mpi block. the time delay between the advanced sys_clk and the distributed sys_clk used to sample cs_n is of no consequence. however, the path delay of cs_n from pad to where is it sampled by sys_clk must be minimized. the calculated delays assume a 100 pf loading on the db pins. figure 21. cpu read transaction table 37 . timing requirements (cpu read transaction) symbol parameter min max unit t pulse minimum pulse width for cs_n 5 ns t addr_max maximum time from negative edge of cs_n to addr valid ? ns t rd_wr_max maximum time from negative edge of cs_n to rd_wr_n falling ? ns t data_max maximum time from negative edge of cs_n to data valid on db port ?6 ns t hiz_max maximum time from rising edge of cs_n to db port going hi-z ?2 ns t access_min minimum time between a read cycle (falling edge of cs_n) and any other transaction (read or write at falling edge of cs_n) 60 ns data valid t access_min t pulse t data_max cpu_cs_n cpu_rd_wr_n cpu_addr[6:0] cpu_data[7:0] t hiz_max t addr_max t rd_wr_max (cs_n) (rd_wr_n) (addr[6:0]) (db[7:0])
orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 55 lattice semiconductor discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm input/output buffer measurement conditions (on-lvds buffer) note: switch to v dd for t plz /t pzl ; switch to gnd for t phz /t pzh . figure 22. ac test loads 5-3233.a(f) figure 23. output buffer delays 5-3235(f) figure 24. input buffer delays 5-3234(f) 50 pf a. load used to measure propagation delay to the output under test to the output under test 50 pf v cc gnd 1 k b. load used to measure rising/falling edges v dd t phh v dd /2 v ss out[i] pa d out 1.5 v 0.0 v t pll pad out[i] ac test loads (shown above) ts[i] out 0.0 v 1.5 v t phh t pll pa d in[i] in 3.0 v v ss v dd /2 v dd pad in in[i]
56 56 lattice semiconductor orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/ fpga output buffer characteristics 5-6865(f) figure 25. sinklim (t j = 25 ?c, v dd = 3.3 v) 5-6867(f) figure 26. slewlim (t j = 25 ?c, v dd = 3.3 v) 5-6867(f) figure 27. fast (t j = 25 ?c, v dd = 3.3 v) 5-6866(f) figure 28. sinklim (t j = 125 ?c, v dd = 3.0 v) 5-6868(f) figure 29. slewlim (t j = 125 ?c, v dd = 3.0 v) 5-6868(f) figure 30. fast (t j = 125 ?c, v dd = 3.0 v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 20 40 60 110 output volta ge , v o (v) i ol 70 50 30 10 i oh output current, i o (ma) 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 40 80 output voltage, v o (v) i ol 100 60 20 i oh output current, i o (ma) 120 140 3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 40 80 output voltage, v o (v) i ol 100 60 20 i oh output current, i o (ma) 120 140 3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 20 40 60 output voltage, v o (v) i ol 70 50 30 10 i oh output current, i o (ma) 80 90 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 40 80 output voltage, v o (v) i ol 100 60 20 i oh output current, i o (ma) 120 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 40 80 output voltage, v o (v) i ol 100 60 20 i oh output current, i o (ma) 120
orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 57 lattice semiconductor discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm lvds buffer characteristics termination resistor the lvds drivers and receivers operate on a 100 differential impedance, as shown below. external resistors are not required. the differential driver and receiver buffers include termination resistors inside the device package as shown in figure 31 below. 5-8703(f) figure 31. lvds driver and receiver and associated internal components lvds driver buffer capabilities under worst-case operating condition, the lvds driver must withstand a disabled or unpowered receiver for an unlimited period of time without being damaged. similarly, when its outputs are short-circuited to each other or to ground, the lvds driver will not suffer permanent damage. figure 32 illustrates the terms associated with lvds driver and receiver pairs. 5-8704(f) figure 32. lvds driver and receiver 5-8705(f) figure 33. lvds driver lvds driver 50 50 lvds receiver center tap device pins 100 external v gpd v oa v ob v ia v ib a b aa bb driver interconnect receiver v oa a v ob b c a c b r load v od = (v oa ?v ob ) v
lattice semiconductor 58 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm estimating power dissipation the total operating power dissipated is estimated by summing the fpga standby (i ddsb ), internal, and external power dissipated, in addition to the embedded block power. table 38 . embedded block power dissipation note: power is calculated assuming an activity factor of 20%. the following discussion relates to the fpga portion of the device. the internal and external power is the power consumed in the plcs and pics, respectively. in general, the standby power is small and may be neglected. the total operating power is as follows: p t = p plc + p pic the internal operating power is made up of two parts: clock generation and pfu output power. the pfu output power can be estimated based upon the number of pfu outputs switching when driving an average fan-out of two: p pfu = 0.078 mw/mhz for each pfu output that switches, 0.136 mw/mhz needs to be multiplied times the frequency (in mhz) that the output switches. generally, this can be estimated by using one-half the clock rate, multiplied by some activity fac- tor; for example, 20%. the power dissipated by the clock generation circuitry is based upon four parts: the ?ed clock power, the power/ clock branch row or column, the clock power dissipated in each pfu that uses this particular clock, and the power from the subset of those pfus that are con?ured as synchronous memory. therefore, the clock power can be cal- culated for the four parts using the following equations: ort4622 clock power p = [0.22 mw/mhz + (0.39 mw/mhz/branch) (# branches) + (0.008 mw/mhz/pfu) (# pfus) + (0.002 mw/mhz/pio (# pios)] for a quick estimate, the worst-case (typical circuit) ort4622 clock power = 4.8 mw/mhz the power dissipated in a pic is the sum of the power dissipated in the four pios in the pic. this consists of power dissipated by inputs and ac power dissipated by outputs. the power dissipated in each pio depends on whether it is con?ured as an input, output, or input/output. if a pio is operating as an output, then there is a power dissipa- tion component for p in , as well as p out . this is because the output feeds back to the input. the power dissipated by an input buffer is (v ih = v dd ? 0.3 v or higher) estimated as: p in = 0.09 mw/mhz the ac power dissipation from an output or bidirectional is estimated by the following: p out = (c l + 8.8 pf) v dd 2 f watts where the unit for c l is farads, and the unit for f is hz. number of active channels operating frequency (hz) estimated power dissipated (watt) min max 1 channel 622 1.08 2 channels 622 1.43 3 channels 622 1.73 4 channels 622 2.01
orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 59 lattice semiconductor discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm pin information this section describes the pins and signals that perform fpga-related functions. during con?uration, the user- programmable i/os are 3-stated and pulled-up with an internal resistor. if any fpga function pin is not used (or not bonded to package pin), it is also 3-stated and pulled-up after con?uration. table 39 . fpga common-function pin description * the orca series 3 fpga data sheet contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other con?uration pins (and the activation of all user i/os) is controlled by a second set of options. symbol i/o description dedicated pins v dd 3.3 v power supply. v dd 2 2.5 v power supply gnd ground supply. reset i during con?uration, reset forces the restart of con?uration and a pull-up is enabled. after con?uration, reset can be used as an fpga logic direct input, which causes all plc latches/ffs to be asynchronously set/reset. cclk i/o in the master and asynchronous peripheral modes, cclk is an output, which strobes con?uration data in. in the slave or synchronous peripheral mode, cclk is input syn- chronous with the data on din or d[7:0]. in microprocessor mode, cclk is used inter- nally and output for daisy-chain operation. done i as an input, a low level on done delays fpga start-up after con?uration.* o as an active-high, open-drain output, a high level on this signal indicates that con?ura- tion is complete. done has a permanent pull-up resistor. prgm i prgm is an active-low input that forces the restart of con?uration and resets the bound- ary-scan circuitry. this pin always has an active pull-up. rd_cfg i this pin must be held high during device initialization until the init pin goes high. this pin always has an active pull-up. during con?uration, rd_cfg is an active-low input that activates the ts_all function and 3-states all of the i/o. after con?uration, rd_cfg can be selected (via a bit stream option) to activate the ts_all function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on rd_cfg will initiate readback of the con?uration data, includ- ing pfu output states, starting with frame address 0. rd_data/tdo o rd_data/tdo is a dual-function pin. if used for readback, rd_data provides con?ura- tion data out. if used in boundary scan, tdo is test data out. special-purpose pins m0, m1, m2 i during powerup and initialization, m0, m1, and m2 are used to select the con?uration mode with their values latched on the rising edge off init . during con?uration, a pull-up is enabled. after con?uration, these pins cannot be user-programmable i/os. m3 i during powerup and initialization, m3 is used to select the speed of the internal oscillator during con?uration with their values latched on the rising edge of init . when m3 is low, the oscillator frequency is 10 mhz. when m3 is high, the oscillator is 1.25 mhz. during con?uration, a pull-up is enabled. i/o after con?uration, this pin is a user-programmable i/o pin.*
lattice semiconductor 60 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm pin information (continued) table 39. fpga common-function pin description (continued) * the orca series 3 fpga data sheet contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other con?uration pins (and the activation of all user i/os) is controlled by a second set of options. symbol i/o description special-purpose pins (continued) tdi, tck, tms i if boundary scan is used, these pins are test data in, test clock, and test mode select inputs. if boundary scan is not selected, all boundary-scan functions are inhibited once con?uration is complete. even if boundary scan is not used, either tck or tms must be held at logic one during con?uration. each pin has a pull-up enabled during con?uration. i/o after con?uration, these pins are user-programmable i/o.* rdy/rclk/ mpi_ale o during con?uration in peripheral mode, rdy/rclk indicates another byte can be written to the fpga. if a read operation is done when the device is selected, the same status is also available on d7 in asynchronous peripheral mode. o during the master parallel con?uration mode, rclk is a read output signal to an external memory. this output is not normally used. i in i960 microprocessor mode, this pin acts as the address latch enable (ale) input. i/o after con?uration, if the mpi is not used, this pin is a user-programmable i/o pin.* hdc o high during con?uration (hdc) is output high until con?uration is complete. it is used as a control output indicating that con?uration is not complete. ldc o low during con?uration (ldc ) is output low until con?uration is complete. it is used as a control output indicating that con?uration is not complete. init i/o init is a bidirectional signal before and during con?uration. during con?uration, a pull-up is enabled, but an external pull-up resistor is recommended. as an active-low open-drain output, init is held low during power stabilization and internal clearing of memory. as an active-low input, init holds the fpga in the wait-state before the start of con?uration. cs0 , cs1 i cs0 and cs1 are used in the asynchronous peripheral, slave parallel, and micropro- cessor con?uration modes. the fpga is selected when cs0 is low and cs1 is high. during con?uration, a pull-up is enabled. i/o after con?uration, these pins are user-programmable i/o pins.* rd /mpi_strb ird is used in the asynchronous peripheral con?uration mode. a low on rd changes d7 into a status output. as a status indication, a high indicates ready, and a low indicates busy. wr and rd should not be used simultaneously. if they are, the write strobe overrides. this pin is also used as the microprocessor interface (mpi) data transfer strobe. for powerpc , it is the transfer start (ts). for i960 , it is the address/data strobe (ads ). i/o after con?uration, if the mpi is not used, this pin is a user-programmable i/o pin.* wr iwr is used in the asynchronous peripheral con?uration mode. when the fpga is selected, a low on the write strobe, wr , loads the data on d[7:0] inputs into an inter- nal data buffer. wr and rd should not be used simultaneously. if they are, the write strobe overrides. i/o after con?uration, this pin is a user-programmable i/o pin.*
orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 61 lattice semiconductor discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm pin information (continued) table 39. fpga common-function pin description (continued) * the orca series 3 fpga data sheet contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other con?uration pins (and the activation of all user i/os) is controlled by a second set of options. symbol i/o description special-purpose pins (continued) mpi_irq o mpi active-low interrupt request output. mpi_bi o powerpc mode mpi burst inhibit output. i/o if the mpi is not in use, this is a user-programmable i/o. mpi_a ck o in powerpc mode mpi operation, this is the active-high transfer acknowledge (t a ) output. for i960 mpi operation, it is the active-low ready/record (rd yrcv ) output. if the mpi is not in use, this is a user-programmable i/o. mpi_rw i in powerpc mode mpi operation, this is the active-low write/active-high read control signals. for i960 operation, it is the active-high write/active-low read control signal. i/o if the mpi is not in use, this is a user-programmable i/o. mpi_clk i this is the clock used for the synchronous mpi interface. for powerpc , it is the clk- out signal. for i960 , it is the system clock that is chosen for the i960 external bus interface. i/o if the mpi is not in use, this is a user-programmable i/o. a[4:0] i for powerpc operation, these are the powerpc address inputs. the address bit mapping (in powerpc /fpga notation) is a[31]/a[0], a[30]/a[1], a[29]/a[2], a[28]/ a[3], a[27]/a[4]. note that a[27]/a[4] is the msb of the address. the a[4:2] inputs are not used in i960 mpi mode. i/o if the mpi is not in use, this is a user-programmable i/o. a[1:0]/mpi_be[1:0] i for i960 operation, mpi_be[1:0] provide the i960 byte enable signals, be[1:0] , that are used as address bits a[1:0] in i960 byte-wide operation. d[7:0] i during peripheral and slave parallel con?uration modes, d[7:0] receive con?ura- tion data, and each pin has a pull-up enabled. during serial con?uration modes, d0 is the din input. d[7:0] are also the data pins for powerpc microprocessor mode and the address/data pins for i960 microprocessor mode. i/o after con?uration, the pins are user-programmable i/o pins.* din i during slave serial or master serial con?uration modes, din accepts serial con?u- ration data synchronous with cclk. during parallel con?uration modes, din is the d0 input. during con?uration, a pull-up is enabled. i/o after con?uration, this pin is a user-programmable i/o pin.* dout o during con?uration, dout is the serial data output that can drive the din of daisy- chained slave lca devices. data out on dout changes on the falling edge of cclk. i/o after con?uration, dout is a user-programmable i/o pin.*
lattice semiconductor 62 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm pin information (continued) this section describes device i/o signals to/from the embedded core excluding the signals at the cic boundary. table 40. fpsc function pin description symbol i/o description hsi lvds pins sts_ina i lvds input receiver a. sts_inan i lvds input receiver a. sts_inb i lvds input receiver b. sts_inbn i lvds input receiver b. sts_inc i lvds input receiver c. sts_incn i lvds input receiver c. sts_ind i lvds input receiver d. sts_indn i lvds input receiver d. sts_outa o lvds output receiver a. sts_outan o lvds output receiver a. sts_outb o lvds output receiver b. sts_outbn o lvds output receiver b. sts_outc o lvds output receiver c. sts_outcn o lvds output receiver c. sts_outd o lvds output receiver d. sts_outdn o lvds output receiver d. ctap_refa lvds input center tap (rx a) (use 0.01 ? to gnd). ctap_refb lvds input center tap (rx b) (use 0.01 ? to gnd). ctap_refc lvds input center tap (rx c) (use 0.01 ? to gnd). ctap_refd lvds input center tap (rx d) (use 0.01 ? to gnd). ref10 i lvds reference voltage: 1.0 v ?3%. ref14 i lvds reference voltage: 1.4 v ?3%. reshi resistor input (use 100 ?1% to reslo input). reslo resistor input. rext reference resistor for pll (10 k to ground). pll_v dd a pll analog v dd (3.3 v 5%). pll_v ss a pll analog v ss (gnd). hsi test signals tstmode i enables cdr test mode. internal pull-down. bypass i enables bypassing of the 622 mhz clock synthesis with tstclk. internal pull-down. tstclk i test clock for emulation of 622 mhz clock during pll bypass. internal pull- down. mreset i test mode reset. internal pull-down. resetrn i resets receiver clock division counter. internal pull-up. resettn i resets transmitter clock division counter. internal pull-up.
orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 63 lattice semiconductor discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm pin information (continued) table 40. fpsc function pin description (continued) * bscan pins-tdi, tdo, tck, and tms are on fpga side. symbol i/o description hsi test signals (continued) tstshftld i enables the test mode control register for shifting in selected tests by a serial port. internal pull-down ecsel i enables external test control of 622 mhz clock phase selection. internal pull-down exdnup i direction of phase change. internal pull-down etoggle i moves 622.08 mhz clock selection on phase per positive pulse. internal pull-down loopbken i enables 622 mbits/s loopback mode. internal pull-down tstphase i controls bypass of 16 pll-generated phases with 16 low-speed phases. internal pull-down tstmux[8:0]s o test mode output port. cpu interface pins db<7:0> i/o cpu interface data bus. internal pull-up. addr<6:0> i cpu interface address bus. internal pull-up. rd_wr_n i cpu interface read/write. internal pull-up. cs_n i chip select. internal pull-up. int_n o interrupt output. internal pull-up. open drain. misc system signals rst_n i reset the core only. the fpga logic is not reset by rst_n. internal pull-down allows chip to stay in reset state when external driver loses power. sys_clk i system clock (77.76 mhz), 50% duty cycle, also the reference clock of pll. internal pull-up. dxp temperature sensing diode (anode +). dxn temperature sensing diode (cathode ?. scan and bscan pins* scan_tstmd i scan test mode input. internal pull-up. scanen i scan mode enable input. internal pull-up. lvds_en i lvds enable used during bscan. during normal operation, lvds_en needs to be pulled high. lvds_en needs to be pulled low for boundary scan. universal bist controller pins sys_dobist i sys_dobist is asserted high to start the bist, and should be kept high dur- ing the entire bist operation. internal pull-down. sys_rssigo o this 32-bit serial out rsb signature consists of the 4-bit fsm state and the bist ?g ?p-?p states from each sbric_rs element. bc o this ?g is asserted to one when bist is complete, and is used for polling the end of bist.
lattice semiconductor 64 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm pin information (continued) in table 41, an input refers to a signal ?wing into the fgpa logic (out of the embedded core) and an output refers to a signal ?wing out of the fpga logic (into the embedded core). table 41. embedded core/fpga interface signal description pin name i/o description data_txa<7:0> o parallel bus of transmitter a. msb is bit 7. data_txa_par o parity for transmitter a. data_txb<7:0> o parallel bus of transmitter b. msb is bit 7. data_txb_par o parity for transmitter b. data_txc<7:0> o parallel bus of transmitter c. msb is bit 7. data_txc_par o parity for transmitter c. data_txd<7:0> o parallel bus of transmitter d. msb is bit 7. data_txd_par o parity for transmitter d. data_rxa<7:0> i parallel bus of receiver a. msb is bit 7. data_rxa_par i parity for parallel bus of receiver a. data_rxa_spe i spe signal for parallel bus of receiver a. data_rxa_c1j1 i c1j1 signal for parallel bus of receiver a. data_rxa_en i enable for parallel bus of receiver a. data_rxb<7:0> i parallel bus of receiver b. msb is bit 7. data_rxb_par i parity for parallel bus of receiver b. data_rxb_spe i spe signal for parallel bus of receiver b. data_rxb_c1j1 i c1j1 signal for parallel bus of receiver b. data_rxb_en i enable for parallel bus of receiver b. data_rxc<7:0> i parallel bus of receiver c. msb is bit 7. data_rxc_par i parity for parallel bus of receiver c. data_rxc_spe i spe signal for parallel bus of receiver c. data_rxc_c1j1 i c1j1 signal for parallel bus of receiver c. data_rxc_en i enable for parallel bus of receiver c. data_rxd<7:0> i parallel bus of receiver d. msb is bit 7. data_rxd_par i parity for parallel bus of receiver d. data_rxd_spe i spe signal for parallel bus of receiver d. data_rxd_c1j1 i c1j1 signal for parallel bus of receiver d. data_rxd_en i enable for parallel bus of receiver d. toh_clk o tx and rx toh serial links clock (25 mhz to 77.76 mhz). toh_txa o toh serial link for transmitter a. toh_txb o toh serial link for transmitter b. toh_txc o toh serial link for transmitter c. toh_txd o toh serial link for transmitter d. tx_toh_ck_en o tx toh serial link clock enable. toh_rxa i toh serial link for receiver a. toh_rxb i toh serial link for receiver b. toh_rxc i toh serial link for receiver c.
orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 65 lattice semiconductor discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm pin information (continued) table 41. embedded core/fpga interface signal description (continued) pin name i/o description toh_rxd i toh serial link for receiver d. rx_toh_ck_en i rx toh serial link clock enable. rx_toh_fp i rx toh serial link frame pulse. toh_ck_fp_en i a soft register bit available to enable rx toh clock and frame pulse. toh_en_a i rx toh enable, soft register. "and" output of resistor channel a enable and hi-z control of toh data output a. cpu_data_tx<7:0> o cpu interface data bus. cpu_data_rx<7:0> i cpu interface data bus. cpu_addr<6:0> o cpu interface address bus. cpu_rd_wr_n o cpu interface read/write. cpu_cs_n o chip select. cpu_int_n i interrupt. sys_fp o system frame pulse for transmitter section. line_fp o line frame pulse for receiver section. fpga_sysclk i system clock (77.76 mhz). prot_sw_a o protection switching control signal. prot_sw_c o protection switching control signal. core_ready i during powerup and fpga con?uration sequence, the core_ready is held low. at the end of fpga con?uration, the core_ready will be held low for six clock (sys_clk) cycles and then go active-high. flag indicates that the embedded core is out of its reset state. ?osync_fp i the alignment fifo synchronizes and locates the data frames and outputs an optimal frame pulse for the four arriving data streams. cdr_clk_a i 77.76 mhz recovered clock for channel a. cdr_clk_b i 77.76 mhz recovered clock for channel b. cdr_clk_c i 77.76 mhz recovered clock for channel c. cdr_clk_d i 77.76 mhz recovered clock for channel d. rb_mp_sel i bit stream selection for microprocessor interface selection. a 0 indicates the microprocessor interface on the core side is selected. a 1 selects the cpu interface from the fpga side.
66 66 lattice semiconductor orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/ pin information (continued) table 42. embedded core/fpga interface signal locations embedded core/fpga interface site fpga input signal fpga output signal asb1a toh_rxa toh_txa asb1b toh_rxb toh_txb asb1c toh_rxc toh_txc asb1d toh_rxd toh_txd cktoasb1 toh_clk asb2a rx_toh_ck_en asb2b rx_toh_fp asb2c toh_ck_fp_en tx_toh_ck_en asb2d toh_en_a asb3a data_rxa7 asb3b data_rxa6 asb3c data_rxa5 asb3d data_rxa4 asb4a data_rxa3 asb4b data_rxa2 asb4c data_rxa1 asb4d data_rxa0 asb5a data_rxa_par prot_sw_a asb5b data_rxa_spe asb5c data_rxa_c1j1 asb5d data_rxa_en asb6a data_rxtb7 asb6b data_rxb6 asb6c data_rxb5 asb6d data_rxb4 asb7a data_rxb3 asb7b data_rxb2 asb7c data_rxb1 asb7d data_rxb0 asb8a data_rxb_par asb8b data_rxb_spe asb8c data_rxb_c1j1 asb8d data_rxb_en asb9a data_rxc7 asb9b data_rxc6 asb9c data_rxc5 asb9d data_rxc4 asb10a data_rxc3 asb10b data_rxc2 embedded core/fpga interface site fpga input signal fpga output signal asb10c data_rxc1 asb10d data_rxc0 asb11a data_rxc_par prot_sw_c asb11b data_rxc_spe asb11c data_rxc_c1j1 asb11d data_rxc_en asb12a data_rxd7 asb12b data_rxd6 asb12c data_rxd5 asb12d data_rxd4 asb13a data_rxd3 asb13b data_rxd2 asb13c data_rxd1 asb13d data_rxd0 asb14a data_rxd_par line_fp asb14b data_rxd_spe sys_fp asb14c data_rxd_c1j1 asb14d data_rxd_en asb15a ?osync_fp data_txa7 asb15b data_txa6 asb15c data_txa5 asb15d data_txa4 asb16a data_txa3 asb16b data_txa2 asb16c data_txa1 asb16d data_txa0 asb17a data_txb7 asb17b data_txb6 asb17c data_txb5 asb17d data_txb4 asb18a data_txb3 asb18b data_txb2 asb18c data_txb1 asb18d data_txb0 asb19a data_txa_par asb19b data_txb_par asb19c data_txc_par asb19d data_txd_par asb20a data_txc7
lattice semiconductor 67 preliminary data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/ pin information (continued) table 42. embedded core/fpga interface signal locations (continued) embedded core/fpga interface site fpga input signal fpga output signal asb20b data_txc6 asb20c data_txc5 asb20d data_txc4 asb21a data_txc3 asb21b data_txc2 asb21c data_txc1 asb21d data_txc0 asb22a data_txd7 asb22b data_txd6 asb22c data_txd5 asb22d data_txd4 asb23a data_txd3 asb23b data_txd2 asb23c data_txd1 asb23d data_txd0 asb24a cpu_data_rx7 cpu_data_tx7 asb24b cpu_data_rx6 cpu_data_tx6 asb24c cpu_data_rx5 cpu_data_tx5 embedded core/fpga interface site fpga input signal fpga output signal asb24d cpu_data_rx4 cpu_data_tx4 asb25a cpu_data_rx3 cpu_data_tx3 asb25b cpu_data_rx2 cpu_data_tx2 asb25c cpu_data_rx1 cpu_data_tx1 asb25d cpu_data_rx0 cpu_data_tx0 asb26a cpu_int_n cpu_addr6 asb26b cpu_addr5 asb26c cpu_addr4 asb26d core_ready cpu_addr3 asb27a cpu_addr2 asb27b cpu_addr1 asb27c cpu_addr0 asb27d cpu_rd_wr_n asb28a cdr_clk_a cpu_cs_n asb28b cdr_clk_b asb28c cdr_clk_c asb28d cdr_clk_d bmlkcntl fpga_sysclk
lattice semiconductor 68 preliminary data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm pin information (continued) the ort4622 is pin compatible with a series 3 or3l125b device in the same package in terms of v dd , v ss , con- ?uration, and special function pins. the uses and characteristics of the fpga user i/o pins in the embedded core area of the device have changed to support the ort4622 functionality. additionally, the lower-left programmable clock manager (pcm) clock input pin (seckll) has been relocated. a "? indicates the pin is not used and must be left unconnected (cannot be tied to v dd or v ss ). table 43 . 432-pin ebga pinout pin ort4622 pad function e4 prd_cfgn rd_cfg d3 pr1d i/o d2 pr1c i/o d1 pr1b i/o f4 pr1a i/o e3 pr2d i/o e2 pr2c i/o e1 pr2b i/o f3 pr2a i/o f2 pr3d i/o f1 pr3c i/o h4 pr3b i/o g3 pr3a i/o-wr g2 pr4d i/o g1 pr4c i/o j4 pr4b i/o h3 v dd 2v dd 2 h2 pr5a i/o j3 pr6c i/o k4 pr6a i/o j2 pr7a i/o-rd /mpi_strb j1 pr8d i/o k3 pr8c i/o k2 pr8b i/o k1 pr8a i/o l3 pr9d i/o m4 pr9c i/o l2 pr9b i/o l1 pr9a i/o-cs0 m3 pr10d i/o n4 pr10a i/o m2 pr11d i/o n3 pr11a i/o-cs1 n2 pr12d i/o p4 pr12c i/o n1 pr12a i/o p3 pr13d i/o p2 pr13c i/o pin ort4622 pad function p1 v dd 2v dd 2 r3 pr14d i/o r2 pr14c i/o r1 pr14b i/o t2 peckr i/o-eckr t4 pr15d i/o t3 pr15c i/o u1 pr15b i/o u2 pr15a i/o u3 pr16d i/o v1 pr16b i/o v2 pr16a i/o v3 pr17d i/o w1 pr17a i/o-m3 v4 pr18d i/o w2 pr18b i/o w3 pr18a i/o y2 w4 pr19a m2 y3 aa1 aa2 y4 aa3 v dd 2v dd 2 ab1 ab2 ab3 ac1 m1 ac2 ab4 ac3 ad2 ad3 ac4 ae1 db3 (core) ae2 db2 (core) ae3 db1 (core) ad4 db0 (core)
lattice semiconductor 69 preliminary data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/ pin information (continued) table 43. 432-pin ebga pinout (continued) pin ort4622 pad function af1 db7 (core) af2 db6 (core) af3 db5 (core) ag1 db4 (core) ag2 v dd 2v dd 2 ag3 int_n (core) af4 ah1 rst_n (core) ah2 m0 ah3 pprgmn prgm ag4 presetn reset ah5 pdone done aj4 rd_wr_n (core) ak4 cs_n (core) al4 addr0 (core) ah6 addr1 (core) aj5 addr2 (core) ak5 addr3 (core) al5 addr4 (core) aj6 addr5 (core) ak6 addr6 (core) al6 tstmux0s (core) ah8 tstmux1s (core) aj7 tstmux2s (core) ak7 tstmux4s (core) al7 tstmux7s (core) ah9 tstmux3s (core) aj8 v dd 2v dd 2 ak8 tstmux6s (core) aj9 tstmux5s (core) ah10 tstmux8s (core) ak9 init al9 tstphase (core) aj10 loopbken (core) ak10 exdnup (core) al10 ecsel (core) aj11 etoggle (core) ah12 resettn (core) ak11 mreset (core) pin ort4622 pad function al11 ldc aj12 tstshftld (core) ah13 resetrn (core) ak12 tstclk (core) aj13 bypass (core) ak13 tstmode (core) ah14 hdc al13 aj14 ak14 sys_clk (core) al14 aj15 v dd 2v dd 2 ak15 sts_outd (core) al15 sts_outdn (core) ak16 ah16 peckb sts_outc (core) aj16 sts_outcn (core) al17 reslo (core) ak17 reshi (core) aj17 al18 ref14 (core) ak18 ref10 (core) aj18 rext (core) al19 pll_v ss a (core) ah18 pll_v dd a (core) ak19 sts_outb (core) aj19 sts_outbn (core) ak20 ah19 sts_outa (core) aj20 sts_outan (core) al21 v dd 2v dd 2 ak21 ctap_refd (core) ah20 sts_ind (core) aj21 sts_indn (core) al22 sts_inc (core) ak22 sts_incn (core) aj22 ctap_refc (core) al23 sts_inb (core) ak23 sts_inbn (core)
70 70 lattice semiconductor orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/ pin information (continued) table 43. 432-pin ebga pinout (continued) pin ort4622 pad function ah22 ctap_refb (core) aj23 sts_ina (core) ak24 sts_inan (core) aj24 ctap_refa (core) ah23 al25 ak25 aj25 lvds_en (core) ah24 scan_tstmd (core) al26 scanen (core) ak26 dxp (core) aj26 dxn (core) al27 v dd 2v dd 2 ak27 sys_dobist (core) aj27 sys_rssigo (core) ah26 bc (core) al28 ak28 aj28 ah27 ag28 pcclk cclk ah29 ah30 ah31 af28 ag29 ag30 ag31 af29 af30 af31 ad28 ae29 v dd 2v dd 2 ae30 ae31 ac28 ad29 ad30 ac29 ab28 pin ort4622 pad function ac30 ac31 ab29 ab30 ab31 aa29 y28 aa30 aa31 y29 mpi_irq w28 y30 pl18a i/o-seckll w29 pl18c i/o w30 pl18d i/o v28 pl17a i/o-mpi_bi w31 pl17c i/o v29 pl17d i/o v30 pl16a i/o v31 pl16c i/o u29 pl16d i/o u30 pl15a i/o-mpi_rw u31 pl15b i/o t30 v dd 2v dd 2 t28 pl15d i/o t29 pl14a i/o-mpi_clk r31 pl14b i/o r30 pl14c i/o r29 peckl i/o-eckl p31 pl13a i/o p30 pl13d i/o p29 pl12a i/o n31 pl12c i/o p28 pl12d i/o n30 pl11a i/o-a4 n29 pl11c i/o m30 pl11d i/o n28 pl10a i/o m29 pl10c i/o l31 v dd 2v dd 2 l30 pl9a i/o-a3
lattice semiconductor 71 preliminary data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/ pin information (continued) table 43. 432-pin ebga pinout (continued) pin ort4622 pad function m28 pl9b i/o l29 pl9c i/o k31 pl9d i/o k30 pl8a i/o-a2 k29 pl8b i/o j31 pl8c i/o j30 pl8d i/o k28 pl7d i/o-a1/mpi_be1 j29 pl6b i/o h30 pl6c i/o h29 pl6d i/o j28 pl5d i/o g31 pl4b i/o g30 pl4c i/o g29 v dd 2v dd 2 h28 pl3a i/o f31 pl3b i/o f30 pl3c i/o f29 pl3d i/o e31 pl2a i/o e30 pl2b i/o e29 pl2c i/o f28 pl2d i/o-a0/mpi_be0 d31 pl1a i/o d30 pl1b i/o d29 pl1c i/o e28 pl1d i/o d27 prd_data rd_data/tdo c28 pt1a i/o-tck b28 pt1b i/o a28 pt1c i/o d26 pt1d i/o c27 pt2a i/o b27 pt2b i/o a27 pt2c i/o c26 pt2d i/o b26 pt3a i/o a26 pt3b i/o d24 pt3c i/o pin ort4622 pad function c25 pt3d i/o b25 pt4a i/o-tms a25 pt4b i/o d23 pt4c i/o c24 pt4d i/o b24 v dd 2v dd 2 c23 pt5b i/o d22 pt5c i/o b23 pt5d i/o a23 pt6a i/o-tdi c22 pt6d i/o b22 pt7a i/o a22 pt7d i/o c21 pt8a i/o d20 pt8d i/o b21 pt9a i/o a21 pt9d i/o c20 pt10a i/o-dout d19 pt10d i/o b20 pt11a i/o c19 pt11c i/o b19 pt11d i/o d18 pt12a i/o-d0/din a19 pt12c i/o c18 pt12d i/o b18 pt13a i/o a18 pt13c i/o c17 pt13d i/o-d1 b17 pt14a i/o-d2 a17 v dd 2v dd 2 b16 pt14c i/o d16 pt14d i/o c16 pt15a i/o-d3 a15 pt15b i/o b15 pt15c i/o c15 peckt i/o-eckt a14 pt16a i/o-d4 b14 pt16b i/o c14 pt16d i/o
72 72 lattice semiconductor orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/ pin information (continued) table 43 . 432-pin ebga pinout (continued) pin ort4622 pad function a13 pt17a i/o d14 pt17b i/o b13 pt17d i/o c13 pt18a i/o-d5 b12 pt18b i/o d13 v dd 2v dd 2 c12 pt19a i/o a11 pt19d i/o b11 pt20a i/o d12 pt20d i/o-d6 c11 pt21a i/o a10 pt21d i/o b10 pt22d i/o c10 pt23b i/o a9 pt23c i/o b9 v dd 2v dd 2 d10 pt24a i/o c9 pt24b i/o b8 pt24c i/o c8 pt24d i/o-d7 d9 pt25a i/o a7 pt25b i/o b7 pt25c i/o c7 pt25d i/o d8 pt26a i/o a6 pt26b i/o b6 pt26c i/o c6 pt26d i/o a5 pt27a i/o-rdy/rclk b5 pt27b i/o c5 pt27c i/o d6 pt27d i/o a4 pt28a i/o b4 pt28b i/o c4 pt28c i/o d5 pt28d i/o-seckur a12 v ss v ss a16 v ss v ss a2 v ss v ss a20 v ss v ss a24 v ss v ss a29 v ss v ss pin ort4622 pad function a3 v ss v ss a30 v ss v ss a8 v ss v ss ad1 v ss v ss ad31 v ss v ss aj1 v ss v ss aj2 v ss v ss aj30 v ss v ss aj31 v ss v ss ak1 v ss v ss ak29 v ss v ss ak3 v ss v ss ak31 v ss v ss al12 v ss v ss al16 v ss v ss al2 v ss v ss al20 v ss v ss al24 v ss v ss al29 v ss v ss al3 v ss v ss al30 v ss v ss al8 v ss v ss b1 v ss v ss b29 v ss v ss b3 v ss v ss b31 v ss v ss c1 v ss v ss c2 v ss v ss c30 v ss v ss c31 v ss v ss h1 v ss v ss h31 v ss v ss m1 v ss v ss m31 v ss v ss t1 v ss v ss t31 v ss v ss y1 v ss v ss y31 v ss v ss a1 v dd v dd a31 v dd v dd aa28 v dd v dd aa4 v dd v dd
lattice semiconductor 73 preliminary data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/ pin information (continued) table 43 . 432-pin ebga pinout (continued) pin ort4622 pad function ae28 v dd v dd ae4 v dd v dd ah11 v dd v dd ah15 v dd v dd ah17 v dd v dd ah21 v dd v dd ah25 v dd v dd ah28 v dd v dd ah4 v dd v dd ah7 v dd v dd aj29 v dd v dd aj3 v dd v dd ak2 v dd v dd ak30 v dd v dd al1 v dd v dd al31 v dd v dd b2 v dd v dd b30 v dd v dd pin ort4622 pad function c29 v dd v dd c3 v dd v dd d11 v dd v dd d15 v dd v dd d17 v dd v dd d21 v dd v dd d25 v dd v dd d28 v dd v dd d4 v dd v dd d7 v dd v dd g28 v dd v dd g4 v dd v dd l28 v dd v dd l4 v dd v dd r28 v dd v dd r4 v dd v dd u28 v dd v dd u4 v dd v dd
74 74 lattice semiconductor orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/ package thermal characteristics summary there are three thermal parameters that are in com- mon use: ja , jc, and jc . it should be noted that all the parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system air?w. ja this is the thermal resistance from junction to ambient (theta-ja, r-theta, etc.). where t j is the junction temperature, t a is the ambient air temperature, and q is the chip power. experimentally, ja is determined when a special ther- mal test die is assembled into the package of interest, and the part is mounted on the thermal test board. the diodes on the test chip are separately calibrated in an oven. the package/board is placed either in a jedec natural convection box or in the wind tunnel, the latter for forced convection measurements. a controlled amount of power (q) is dissipated in the test chips heater resistor, the chips temperature (t j ) is deter- mined by the forward drop on the diodes, and the ambi- ent temperature (t a ) is noted. note that ja is expressed in units of ?/watt. jc this jedec designated parameter correlates the junc- tion temperature to the case temperature. it is generally used to infer the junction temperature while the device is operating in the system. it is not considered a true thermal resistance, and it is de?ed by: where t c is the case temperature at top dead center, t j is the junction temperature, and q is the chip power. during the ja measurements described above, besides the other parameters measured, an additional temperature reading, t c , is made with a thermocouple attached at top-dead-center of the case. jc is also expressed in units of ?/w. jc this is the thermal resistance from junction to case. it is most often used when attaching a heat sink to the top of the package. it is de?ed by: the parameters in this equation have been de?ed above. however, the measurements are performed with the case of the part pressed against a water- cooled heat sink to draw most of the heat generated by the chip out the top of the package. it is this difference in the measurement process that differentiates jc from jc. jc is a true thermal resistance and is expressed in units of ?/w. jb this is the thermal resistance from junction to board ( jl ). it is de?ed by: where t b is the temperature of the board adjacent to a lead measured with a thermocouple. the other param- eters on the right-hand side have been de?ed above. this is considered a true thermal resistance, and the measurement is made with a water-cooled heat sink pressed against the board to draw most of the heat out of the leads. note that jb is expressed in units of ?/w, and that this parameter and the way it is mea- sured are still in jedec committee. fpga maximum junction temperature once the power dissipated by the fpga has been determined (see the estimating power dissipation sec- tion), the maximum junction temperature of the fpga can be found. this is needed to determine if speed der- ating of the device from the 85 ? junction temperature used in all of the delay tables is needed. using the maximum ambient temperature, t amax , and the power dissipated by the device, q (expressed in ?), the max- imum junction temperature is approximated by: t jmax = t amax + (q ? ja ) table 44 lists the thermal characteristics for all pack- ages used with the orca ort4622 series of fpgas. ja t j t a q ------------------- - = jc t j t c q -------------------- = jc t j t c q -------------------- = jb t j t b q ------------------- - =
lattice semiconductor 75 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm package thermal characteristics table 44 . orca ort4622 plastic package thermal guidelines package coplanarity the coplanarity limits of the orca series 3/3+ packages are as follows: ebga: 8.0 mils package parasitics the electrical performance of an ic package, such as signal quality and noise sensitivity, is directly affected by the package parasitics. table 45 lists eight parasitics associated with the orca packages. these parasitics represent the contributions of all components of a package, which include the bond wires, all internal package routing, and the external leads. four inductances in nh are listed: l sw and l sl, the self-inductance of the lead; and l mw and l ml , the mutual inductance to the nearest neighbor lead. these parameters are important in determining ground bounce noise and inductive crosstalk noise. three capacitances in pf are listed: c m , the mutual capacitance of the lead to the near- est neighbor lead; and c 1 and c 2 , the total capacitance of the lead to all other leads (all other leads are assumed to be grounded). these parameters are important in determining capacitive crosstalk and the capacitive loading effect of the lead. resistance values are in m . the parasitic values in table 45 are for the circuit model of bond wire and package lead parasitics. if the mutual capacitance value is not used in the designers model, then the value listed as mutual capacitance should be added to each of the c 1 and c 2 capacitors. package ja ( c/w) t = 70 c max t j = 125 c max 0 fpm (w) 0 fpm 200 fpm 500 fpm 432-pin ebga 11 8.5 5 5
orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 76 lattice semiconductor discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm package parasitics (continued) table 45. orca ort4622 package parasitics 5-3862(c)r2 figure 34. package parasitics package type l sw l mw r w c 1 c 2 c m l sl l ml 432-pin ebga 4 1.5 500 1.0 1.0 0.3 3?.5 0.5? pad n l sw r w circuit board pad c m c 1 l sw r w l sl l mw c 2 c 1 l ml c 2 l sl pad n + 1
lattice semiconductor 77 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm package outline diagram terms and denitions basic size (bsc): the basic size of a dimension is the size from which the limits for that dimension are derived by the application of the allowance and the tolerance. design size: the design size of a dimension is the actual size of the design, including an allowance for ? and tolerance. typical (typ): when speci?d after a dimension, this indicates the repeated design size if a tolerance is speci?d or repeated basic size if a tolerance is not speci?d. reference (ref): the reference dimension is an untoleranced dimension used for informational purposes only. it is a repeated dimension or one that can be derived from other values in the drawing. minimum (min) or maximum (max): indicates the minimum or maximum allowable size of a dimension.
orca ort4622 fpsc data sheet four-channel x 622 mbits/s backplane transceiver july 2009 78 lattice semiconductor discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm package outline diagram (continued) 432-pin ebga dimensions are in millimeters. 5-4406(f) 0.91 0.06 1.54 0.13 seating plane solder ball 0.63 0.07 0.20 40.00 0.10 40.00 a1 ball m d ag b f k h g e ad l t j n aj c y p ah ae ac aa w u r ak af ab v al a 19 30 26 5 28 24 22 23 25 7 20 31 29 15 21 18 327 11 17 4 6 8 10 12 14 16 2 913 1 30 spaces @ 1.27 = 38.10 30 spaces a1 ball 0.75 0.15 identifier zone 0.10 @ 1.27 = 38.10 corner
lattice semiconductor 79 data sheet orca ort4622 fpsc july 2009 four-channel x 622 mbits/s backplane transceiver discontinued product (pcn#03-08). contact rochester electronics for availability. www.latticesemi.com/sales/discontinueddevicessales.cfm ordering information table 46. ordering information device family part number package type ball count grade packing designator ort4622 ORT4622BC432-DB ebga 432 c db device family ort4622 ort4622 x xx xx xxx packing designator db = dry packed tray package type bc = enhanced ball grid array (ebga) ball count 432 grade blank = industrial

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